drm/i915/gt: Convert the leftover for_each_engine(gt)
diff mbox series

Message ID 20191018115331.8980-1-chris@chris-wilson.co.uk
State New
Headers show
Series
  • drm/i915/gt: Convert the leftover for_each_engine(gt)
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Commit Message

Chris Wilson Oct. 18, 2019, 11:53 a.m. UTC
Use the local gt for iterating over the available set of engines.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_rc6.c        | 12 ++++++------
 drivers/gpu/drm/i915/gt/intel_ringbuffer.c |  6 +++---
 drivers/gpu/drm/i915/i915_gem_gtt.c        |  2 +-
 drivers/gpu/drm/i915/i915_pmu.c            |  2 +-
 4 files changed, 11 insertions(+), 11 deletions(-)

Comments

Tvrtko Ursulin Oct. 18, 2019, 12:13 p.m. UTC | #1
On 18/10/2019 12:53, Chris Wilson wrote:
> Use the local gt for iterating over the available set of engines.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_rc6.c        | 12 ++++++------
>   drivers/gpu/drm/i915/gt/intel_ringbuffer.c |  6 +++---
>   drivers/gpu/drm/i915/i915_gem_gtt.c        |  2 +-
>   drivers/gpu/drm/i915/i915_pmu.c            |  2 +-
>   4 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 71184aa72896..70f0e01a38b9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -65,7 +65,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
>   
>   	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>   	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> -	for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
> +	for_each_engine(engine, rc6_to_gt(rc6), id)
>   		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>   
>   	set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
> @@ -133,7 +133,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
>   
>   	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>   	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> -	for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
> +	for_each_engine(engine, rc6_to_gt(rc6), id)
>   		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>   
>   	set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
> @@ -192,7 +192,7 @@ static void gen8_rc6_enable(struct intel_rc6 *rc6)
>   	set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
>   	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>   	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> -	for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
> +	for_each_engine(engine, rc6_to_gt(rc6), id)
>   		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>   	set(uncore, GEN6_RC_SLEEP, 0);
>   	set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
> @@ -219,7 +219,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
>   	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
>   	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
>   
> -	for_each_engine(engine, i915, id)
> +	for_each_engine(engine, rc6_to_gt(rc6), id)
>   		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>   
>   	set(uncore, GEN6_RC_SLEEP, 0);
> @@ -344,7 +344,7 @@ static void chv_rc6_enable(struct intel_rc6 *rc6)
>   	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>   	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>   
> -	for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
> +	for_each_engine(engine, rc6_to_gt(rc6), id)
>   		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>   	set(uncore, GEN6_RC_SLEEP, 0);
>   
> @@ -371,7 +371,7 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6)
>   	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
>   	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
>   
> -	for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
> +	for_each_engine(engine, rc6_to_gt(rc6), id)
>   		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>   
>   	set(uncore, GEN6_RC6_THRESHOLD, 0x557);
> diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
> index 311fdc0a21bc..bf631f15aa78 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
> @@ -1609,7 +1609,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
>   			struct intel_engine_cs *signaller;
>   
>   			*cs++ = MI_LOAD_REGISTER_IMM(num_engines);
> -			for_each_engine(signaller, i915, id) {
> +			for_each_engine(signaller, engine->gt, id) {
>   				if (signaller == engine)
>   					continue;
>   
> @@ -1663,7 +1663,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
>   			i915_reg_t last_reg = {}; /* keep gcc quiet */
>   
>   			*cs++ = MI_LOAD_REGISTER_IMM(num_engines);
> -			for_each_engine(signaller, i915, id) {
> +			for_each_engine(signaller, engine->gt, id) {
>   				if (signaller == engine)
>   					continue;
>   
> @@ -1676,7 +1676,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
>   			/* Insert a delay before the next switch! */
>   			*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
>   			*cs++ = i915_mmio_reg_offset(last_reg);
> -			*cs++ = intel_gt_scratch_offset(rq->engine->gt,
> +			*cs++ = intel_gt_scratch_offset(engine->gt,
>   							INTEL_GT_SCRATCH_FIELD_DEFAULT);
>   			*cs++ = MI_NOOP;
>   		}
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 0df057838a24..3148d5946b63 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1569,7 +1569,7 @@ static void gen7_ppgtt_enable(struct intel_gt *gt)
>   	}
>   	intel_uncore_write(uncore, GAM_ECOCHK, ecochk);
>   
> -	for_each_engine(engine, i915, id) {
> +	for_each_engine(engine, gt, id) {
>   		/* GFX_MODE is per-ring on gen7+ */
>   		ENGINE_WRITE(engine,
>   			     RING_MODE_GEN7,
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 144c32eed045..85912917c062 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -301,7 +301,7 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns)
>   	if ((i915->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
>   		return;
>   
> -	for_each_engine(engine, i915, id) {
> +	for_each_engine(engine, gt, id) {
>   		struct intel_engine_pmu *pmu = &engine->pmu;
>   		unsigned long flags;
>   		bool busy;
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 71184aa72896..70f0e01a38b9 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -65,7 +65,7 @@  static void gen11_rc6_enable(struct intel_rc6 *rc6)
 
 	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
 	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
-	for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
+	for_each_engine(engine, rc6_to_gt(rc6), id)
 		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
 
 	set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
@@ -133,7 +133,7 @@  static void gen9_rc6_enable(struct intel_rc6 *rc6)
 
 	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
 	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
-	for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
+	for_each_engine(engine, rc6_to_gt(rc6), id)
 		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
 
 	set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
@@ -192,7 +192,7 @@  static void gen8_rc6_enable(struct intel_rc6 *rc6)
 	set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
 	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
 	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
-	for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
+	for_each_engine(engine, rc6_to_gt(rc6), id)
 		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
 	set(uncore, GEN6_RC_SLEEP, 0);
 	set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
@@ -219,7 +219,7 @@  static void gen6_rc6_enable(struct intel_rc6 *rc6)
 	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
 	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
 
-	for_each_engine(engine, i915, id)
+	for_each_engine(engine, rc6_to_gt(rc6), id)
 		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
 
 	set(uncore, GEN6_RC_SLEEP, 0);
@@ -344,7 +344,7 @@  static void chv_rc6_enable(struct intel_rc6 *rc6)
 	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
 	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
 
-	for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
+	for_each_engine(engine, rc6_to_gt(rc6), id)
 		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
 	set(uncore, GEN6_RC_SLEEP, 0);
 
@@ -371,7 +371,7 @@  static void vlv_rc6_enable(struct intel_rc6 *rc6)
 	set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
 	set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
 
-	for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
+	for_each_engine(engine, rc6_to_gt(rc6), id)
 		set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
 
 	set(uncore, GEN6_RC6_THRESHOLD, 0x557);
diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index 311fdc0a21bc..bf631f15aa78 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -1609,7 +1609,7 @@  static inline int mi_set_context(struct i915_request *rq, u32 flags)
 			struct intel_engine_cs *signaller;
 
 			*cs++ = MI_LOAD_REGISTER_IMM(num_engines);
-			for_each_engine(signaller, i915, id) {
+			for_each_engine(signaller, engine->gt, id) {
 				if (signaller == engine)
 					continue;
 
@@ -1663,7 +1663,7 @@  static inline int mi_set_context(struct i915_request *rq, u32 flags)
 			i915_reg_t last_reg = {}; /* keep gcc quiet */
 
 			*cs++ = MI_LOAD_REGISTER_IMM(num_engines);
-			for_each_engine(signaller, i915, id) {
+			for_each_engine(signaller, engine->gt, id) {
 				if (signaller == engine)
 					continue;
 
@@ -1676,7 +1676,7 @@  static inline int mi_set_context(struct i915_request *rq, u32 flags)
 			/* Insert a delay before the next switch! */
 			*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
 			*cs++ = i915_mmio_reg_offset(last_reg);
-			*cs++ = intel_gt_scratch_offset(rq->engine->gt,
+			*cs++ = intel_gt_scratch_offset(engine->gt,
 							INTEL_GT_SCRATCH_FIELD_DEFAULT);
 			*cs++ = MI_NOOP;
 		}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 0df057838a24..3148d5946b63 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1569,7 +1569,7 @@  static void gen7_ppgtt_enable(struct intel_gt *gt)
 	}
 	intel_uncore_write(uncore, GAM_ECOCHK, ecochk);
 
-	for_each_engine(engine, i915, id) {
+	for_each_engine(engine, gt, id) {
 		/* GFX_MODE is per-ring on gen7+ */
 		ENGINE_WRITE(engine,
 			     RING_MODE_GEN7,
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 144c32eed045..85912917c062 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -301,7 +301,7 @@  engines_sample(struct intel_gt *gt, unsigned int period_ns)
 	if ((i915->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
 		return;
 
-	for_each_engine(engine, i915, id) {
+	for_each_engine(engine, gt, id) {
 		struct intel_engine_pmu *pmu = &engine->pmu;
 		unsigned long flags;
 		bool busy;