[5/5] arm64: zynqmp: Add data cells to access efuse
diff mbox series

Message ID 20191018160735.15658-6-m.tretter@pengutronix.de
State New
Headers show
Series
  • arm64: zynqmp: add firmware device tree node
Related show

Commit Message

Michael Tretter Oct. 18, 2019, 4:07 p.m. UTC
From: Durga Challa <vnsl.durga.challa@xilinx.com>

This patch adds data cells under nvmem node to
read efuse memory

Signed-off-by: Durga Challa <vnsl.durga.challa@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 48 ++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

Comments

Michal Simek Oct. 23, 2019, 12:30 p.m. UTC | #1
On 18. 10. 19 18:07, Michael Tretter wrote:
> From: Durga Challa <vnsl.durga.challa@xilinx.com>
> 
> This patch adds data cells under nvmem node to
> read efuse memory
> 
> Signed-off-by: Durga Challa <vnsl.durga.challa@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
> ---
>  arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 48 ++++++++++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index 3c731e73903a..73d26177eb96 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -128,6 +128,54 @@
>  				soc_revision: soc_revision@0 {
>  					reg = <0x0 0x4>;
>  				};
> +				efuse_dna: efuse_dna@c {
> +					reg = <0xc 0xc>;
> +				};
> +				efuse_usr0: efuse_usr0@20 {
> +					reg = <0x20 0x4>;
> +				};
> +				efuse_usr1: efuse_usr1@24 {
> +					reg = <0x24 0x4>;
> +				};
> +				efuse_usr2: efuse_usr2@28 {
> +					reg = <0x28 0x4>;
> +				};
> +				efuse_usr3: efuse_usr3@2c {
> +					reg = <0x2c 0x4>;
> +				};
> +				efuse_usr4: efuse_usr4@30 {
> +					reg = <0x30 0x4>;
> +				};
> +				efuse_usr5: efuse_usr5@34 {
> +					reg = <0x34 0x4>;
> +				};
> +				efuse_usr6: efuse_usr6@38 {
> +					reg = <0x38 0x4>;
> +				};
> +				efuse_usr7: efuse_usr7@3c {
> +					reg = <0x3c 0x4>;
> +				};
> +				efuse_miscusr: efuse_miscusr@40 {
> +					reg = <0x40 0x4>;
> +				};
> +				efuse_chash: efuse_chash@50 {
> +					reg = <0x50 0x4>;
> +				};
> +				efuse_pufmisc: efuse_pufmisc@54 {
> +					reg = <0x54 0x4>;
> +				};
> +				efuse_sec: efuse_sec@58 {
> +					reg = <0x58 0x4>;
> +				};
> +				efuse_spkid: efuse_spkid@5c {
> +					reg = <0x5c 0x4>;
> +				};
> +				efuse_ppk0hash: efuse_ppk0hash@a0 {
> +					reg = <0xa0 0x30>;
> +				};
> +				efuse_ppk1hash: efuse_ppk1hash@d0 {
> +					reg = <0xd0 0x30>;
> +				};
>  			};
>  
>  			zynqmp_pcap: pcap {
> 

This code is not in mainline yet that's why I am ignoring this patch.

Thanks,
Michal

Patch
diff mbox series

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 3c731e73903a..73d26177eb96 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -128,6 +128,54 @@ 
 				soc_revision: soc_revision@0 {
 					reg = <0x0 0x4>;
 				};
+				efuse_dna: efuse_dna@c {
+					reg = <0xc 0xc>;
+				};
+				efuse_usr0: efuse_usr0@20 {
+					reg = <0x20 0x4>;
+				};
+				efuse_usr1: efuse_usr1@24 {
+					reg = <0x24 0x4>;
+				};
+				efuse_usr2: efuse_usr2@28 {
+					reg = <0x28 0x4>;
+				};
+				efuse_usr3: efuse_usr3@2c {
+					reg = <0x2c 0x4>;
+				};
+				efuse_usr4: efuse_usr4@30 {
+					reg = <0x30 0x4>;
+				};
+				efuse_usr5: efuse_usr5@34 {
+					reg = <0x34 0x4>;
+				};
+				efuse_usr6: efuse_usr6@38 {
+					reg = <0x38 0x4>;
+				};
+				efuse_usr7: efuse_usr7@3c {
+					reg = <0x3c 0x4>;
+				};
+				efuse_miscusr: efuse_miscusr@40 {
+					reg = <0x40 0x4>;
+				};
+				efuse_chash: efuse_chash@50 {
+					reg = <0x50 0x4>;
+				};
+				efuse_pufmisc: efuse_pufmisc@54 {
+					reg = <0x54 0x4>;
+				};
+				efuse_sec: efuse_sec@58 {
+					reg = <0x58 0x4>;
+				};
+				efuse_spkid: efuse_spkid@5c {
+					reg = <0x5c 0x4>;
+				};
+				efuse_ppk0hash: efuse_ppk0hash@a0 {
+					reg = <0xa0 0x30>;
+				};
+				efuse_ppk1hash: efuse_ppk1hash@d0 {
+					reg = <0xd0 0x30>;
+				};
 			};
 
 			zynqmp_pcap: pcap {