| Message ID | 20191022075151.5781-2-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm/i915/selftests: Add coverage of mocs registers | expand |
Quoting Chris Wilson (2019-10-22 08:51:51) > On my kbl gt4e, there is a distinction between the power context and the > normal contexts. We must delay the mocs setup until after we have primed > the kernel context to record the mocs register settings within the > context image. > > Fixes: eca0b7208969 ("drm/i915: Do initial mocs configuration directly") > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Hmm, after sending the patch, I reran the tests and it had lost the l3cc configuration again. Problem not solved. -Chris
Quoting Chris Wilson (2019-10-22 08:56:32) > Quoting Chris Wilson (2019-10-22 08:51:51) > > On my kbl gt4e, there is a distinction between the power context and the > > normal contexts. We must delay the mocs setup until after we have primed > > the kernel context to record the mocs register settings within the > > context image. > > > > Fixes: eca0b7208969 ("drm/i915: Do initial mocs configuration directly") > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> > > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > > Hmm, after sending the patch, I reran the tests and it had lost the l3cc > configuration again. Problem not solved. So the secret is I need both this deferral and emission within context. Existing sequence or either change alone is not enough!!! -Chris
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c index 06e73d56cfcf..0f9be5722c24 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c @@ -12,6 +12,7 @@ #include "intel_gt.h" #include "intel_gt_pm.h" #include "intel_gt_requests.h" +#include "intel_mocs.h" #include "intel_pm.h" #include "intel_rc6.h" #include "intel_wakeref.h" @@ -182,13 +183,16 @@ int intel_gt_resume(struct intel_gt *gt) engine->serial++; /* kernel context lost */ err = engine->resume(engine); - intel_engine_pm_put(engine); + intel_engine_pm_put(engine); /* primes kernel context */ if (err) { dev_err(gt->i915->drm.dev, "Failed to restart %s (%d)\n", engine->name, err); break; } + intel_engine_flush_submission(engine); + + intel_mocs_init_engine(engine); } intel_rc6_enable(>->rc6); diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index f9f3e985bb79..53ee389453d5 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -143,7 +143,6 @@ #include "intel_gt.h" #include "intel_gt_pm.h" #include "intel_lrc_reg.h" -#include "intel_mocs.h" #include "intel_reset.h" #include "intel_workarounds.h" @@ -2639,8 +2638,6 @@ static int execlists_resume(struct intel_engine_cs *engine) intel_engine_apply_workarounds(engine); intel_engine_apply_whitelist(engine); - intel_mocs_init_engine(engine); - intel_engine_reset_breadcrumbs(engine); if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) {
On my kbl gt4e, there is a distinction between the power context and the normal contexts. We must delay the mocs setup until after we have primed the kernel context to record the mocs register settings within the context image. Fixes: eca0b7208969 ("drm/i915: Do initial mocs configuration directly") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 +++++- drivers/gpu/drm/i915/gt/intel_lrc.c | 3 --- 2 files changed, 5 insertions(+), 4 deletions(-)