[5/8] drm/i915: Use drm_rect to store the pfit window pos/size

Message ID	20191022175554.18012-6-ville.syrjala@linux.intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=R1YD=YP=lists.freedesktop.org=intel-gfx-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EE7F420659 From: Ville Syrjala <ville.syrjala@linux.intel.com> To: intel-gfx@lists.freedesktop.org Date: Tue, 22 Oct 2019 20:55:51 +0300 Message-Id: <20191022175554.18012-6-ville.syrjala@linux.intel.com> In-Reply-To: <20191022175554.18012-1-ville.syrjala@linux.intel.com> References: <20191022175554.18012-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/8] drm/i915: Use drm_rect to store the pfit window pos/size Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	drm/i915: pfit/scaler rework prep stuff \| expand [0/8] drm/i915: pfit/scaler rework prep stuff [1/8] drm/i915: Parametrize PFIT_PIPE [2/8] drm/i915: Replace some accidental I915_READ_FW()s with the normal version [3/8] drm/i915: Fix skl+ non-scaled pfit modes [4/8] drm/i915: Flatten a bunch of the pfit functions [5/8] drm/i915: Use drm_rect to store the pfit window pos/size [6/8] drm/i915: s/pipe_config/crtc_state/ in pfit functions [7/8] drm/i915: Pass connector state to pfit calculations [8/8] drm/i915: Have pfit calculations return an error code

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 6aeec01e2d24..38df154123d2 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5521,10 +5521,8 @@ static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state) int width, height; if (crtc_state->pch_pfit.enabled) { - u32 pfit_size = crtc_state->pch_pfit.size; - - width = pfit_size >> 16; - height = pfit_size & 0xffff; + width = drm_rect_width(&crtc_state->pch_pfit.dst); + height = drm_rect_height(&crtc_state->pch_pfit.dst); } else { width = adjusted_mode->crtc_hdisplay; height = adjusted_mode->crtc_vdisplay; @@ -5633,11 +5631,20 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum pipe pipe = crtc->pipe; const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; + struct drm_rect src = { + .x2 = crtc_state->pipe_src_w << 16, + .y2 = crtc_state->pipe_src_h << 16, + }; + const struct drm_rect *dst = &crtc_state->pch_pfit.dst; u16 uv_rgb_hphase, uv_rgb_vphase; - int pfit_w, pfit_h, hscale, vscale; + enum pipe pipe = crtc->pipe; + int width = drm_rect_width(dst); + int height = drm_rect_height(dst); + int x = dst->x1; + int y = dst->y1; + int hscale, vscale; int id; if (!crtc_state->pch_pfit.enabled) @@ -5646,11 +5653,8 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state) if (WARN_ON(crtc_state->scaler_state.scaler_id < 0)) return; - pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF; - pfit_h = crtc_state->pch_pfit.size & 0xFFFF; - - hscale = (crtc_state->pipe_src_w << 16) / pfit_w; - vscale = (crtc_state->pipe_src_h << 16) / pfit_h; + hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX); + vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX); uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false); uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); @@ -5662,15 +5666,20 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state) PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); I915_WRITE(SKL_PS_HPHASE(pipe, id), PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); - I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos); - I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size); + I915_WRITE(SKL_PS_WIN_POS(pipe, id), x << 16 | y); + I915_WRITE(SKL_PS_WIN_SZ(pipe, id), width << 16 | height); } static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_rect *dst = &crtc_state->pch_pfit.dst; enum pipe pipe = crtc->pipe; + int width = drm_rect_width(dst); + int height = drm_rect_height(dst); + int x = dst->x1; + int y = dst->y1; if (!crtc_state->pch_pfit.enabled) return; @@ -5684,8 +5693,8 @@ static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state) PF_PIPE_SEL_IVB(pipe)); else I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); - I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos); - I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size); + I915_WRITE(PF_WIN_POS(pipe), x << 16 | y); + I915_WRITE(PF_WIN_SZ(pipe), width << 16 | height); } void hsw_enable_ips(const struct intel_crtc_state *crtc_state) @@ -7400,8 +7409,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) { u32 pixel_rate = crtc_state->base.adjusted_mode.crtc_clock; - u32 pfit_size = crtc_state->pch_pfit.size; - u64 pipe_w, pipe_h, pfit_w, pfit_h; + unsigned int pipe_w, pipe_h, pfit_w, pfit_h; /* * We only use IF-ID interlacing. If we ever use @@ -7414,8 +7422,9 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) pipe_w = crtc_state->pipe_src_w; pipe_h = crtc_state->pipe_src_h; - pfit_w = (pfit_size >> 16) & 0xFFFF; - pfit_h = pfit_size & 0xFFFF; + pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst); + pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst); + if (pipe_w < pfit_w) pipe_w = pfit_w; if (pipe_h < pfit_h) @@ -9809,6 +9818,14 @@ static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, &pipe_config->fdi_m_n, NULL); } +static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, + u32 pos, u32 size) +{ + drm_rect_init(&crtc_state->pch_pfit.dst, + pos >> 16, pos & 0xffff, + size >> 16, size & 0xffff); +} + static void skylake_get_pfit_config(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); @@ -9827,8 +9844,11 @@ static void skylake_get_pfit_config(struct intel_crtc_state *crtc_state) id = i; crtc_state->pch_pfit.enabled = true; - crtc_state->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); - crtc_state->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); + + ilk_get_pfit_pos_size(crtc_state, + I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)), + I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i))); + scaler_state->scalers[i].in_use = true; break; } @@ -9986,8 +10006,10 @@ static void ironlake_get_pfit_config(struct intel_crtc_state *crtc_state) (tmp & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); crtc_state->pch_pfit.enabled = true; - crtc_state->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); - crtc_state->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); + + ilk_get_pfit_pos_size(crtc_state, + I915_READ(PF_WIN_POS(crtc->pipe)), + I915_READ(PF_WIN_SZ(crtc->pipe))); } static bool ironlake_get_pipe_config(struct intel_crtc *crtc, @@ -12383,9 +12405,8 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, pipe_config->gmch_pfit.pgm_ratios, pipe_config->gmch_pfit.lvds_border_bits); else - DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n", - pipe_config->pch_pfit.pos, - pipe_config->pch_pfit.size, + DRM_DEBUG_KMS("pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", + DRM_RECT_ARG(&pipe_config->pch_pfit.dst), enableddisabled(pipe_config->pch_pfit.enabled), yesno(pipe_config->pch_pfit.force_thru)); @@ -13058,8 +13079,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); if (current_config->pch_pfit.enabled) { - PIPE_CONF_CHECK_X(pch_pfit.pos); - PIPE_CONF_CHECK_X(pch_pfit.size); + PIPE_CONF_CHECK_I(pch_pfit.dst.x1); + PIPE_CONF_CHECK_I(pch_pfit.dst.y1); + PIPE_CONF_CHECK_I(pch_pfit.dst.x2); + PIPE_CONF_CHECK_I(pch_pfit.dst.y2); } PIPE_CONF_CHECK_I(scaler_state.scaler_id); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 8358152e403e..ab4ec6215c22 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -902,8 +902,7 @@ struct intel_crtc_state { /* Panel fitter placement and size for Ironlake+ */ struct { - u32 pos; - u32 size; + struct drm_rect dst; bool enabled; bool force_thru; } pch_pfit; diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 4601416c603e..68257b21abf5 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -179,13 +179,13 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc, int fitting_mode) { const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; - int x = 0, y = 0, width = 0, height = 0; + int x, y, width, height; /* Native modes don't need fitting */ if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w && adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h && pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420) - goto done; + return; switch (fitting_mode) { case DRM_MODE_SCALE_CENTER: @@ -231,14 +231,13 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc, break; default: - WARN(1, "bad panel fit mode: %d\n", fitting_mode); + MISSING_CASE(fitting_mode); return; } -done: - pipe_config->pch_pfit.pos = (x << 16) | y; - pipe_config->pch_pfit.size = (width << 16) | height; - pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0; + drm_rect_init(&pipe_config->pch_pfit.dst, + x, y, width, height); + pipe_config->pch_pfit.enabled = true; } static void diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 80ea5074cabd..e7ce80acdd45 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4102,7 +4102,6 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state) { uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1); u32 src_w, src_h, dst_w, dst_h; - u32 pfit_size = crtc_state->pch_pfit.size; uint_fixed_16_16_t fp_w_ratio, fp_h_ratio; uint_fixed_16_16_t downscale_h, downscale_w; @@ -4112,8 +4111,8 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state) src_w = crtc_state->pipe_src_w; src_h = crtc_state->pipe_src_h; - dst_w = pfit_size >> 16; - dst_h = pfit_size & 0xffff; + dst_w = drm_rect_width(&crtc_state->pch_pfit.dst); + dst_h = drm_rect_height(&crtc_state->pch_pfit.dst); if (!dst_w || !dst_h) return pipe_downscale;

[5/8] drm/i915: Use drm_rect to store the pfit window pos/size

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