| Message ID | 1571985126-34393-1-git-send-email-zhangshaokun@hisilicon.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 7db3e57e6a95435cef5b33f2a90efcac5ce577da |
| Headers | show |
| Series | arm64: cpufeature: Fix typos in comment | expand |
On 10/25/2019 07:32 AM, Shaokun Zhang wrote: > Fix up one typos: CTR_E0 -> CTR_EL0 > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com> > Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> > --- > arch/arm64/kernel/cpuinfo.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c > index 05933c065732..56bba746da1c 100644 > --- a/arch/arm64/kernel/cpuinfo.c > +++ b/arch/arm64/kernel/cpuinfo.c > @@ -329,7 +329,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) > info->reg_cntfrq = arch_timer_get_cntfrq(); > /* > * Use the effective value of the CTR_EL0 than the raw value > - * exposed by the CPU. CTR_E0.IDC field value must be interpreted > + * exposed by the CPU. CTR_EL0.IDC field value must be interpreted > * with the CLIDR_EL1 fields to avoid triggering false warnings > * when there is a mismatch across the CPUs. Keep track of the > * effective value of the CTR_EL0 in our internal records for > Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
On Fri, Oct 25, 2019 at 02:32:06PM +0800, Shaokun Zhang wrote: > Fix up one typos: CTR_E0 -> CTR_EL0 > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com> > Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> > --- Queued for 5.5. Thanks.
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 05933c065732..56bba746da1c 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -329,7 +329,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) info->reg_cntfrq = arch_timer_get_cntfrq(); /* * Use the effective value of the CTR_EL0 than the raw value - * exposed by the CPU. CTR_E0.IDC field value must be interpreted + * exposed by the CPU. CTR_EL0.IDC field value must be interpreted * with the CLIDR_EL1 fields to avoid triggering false warnings * when there is a mismatch across the CPUs. Keep track of the * effective value of the CTR_EL0 in our internal records for
Fix up one typos: CTR_E0 -> CTR_EL0 Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> --- arch/arm64/kernel/cpuinfo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)