Message ID | 20191026061736.22594-1-chris@chris-wilson.co.uk (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | drm/i915/tgl: Adjust the location of RING_MI_MODE in the context image | expand |
On Sat, Oct 26, 2019 at 07:17:36AM +0100, Chris Wilson wrote: > The location of RING_MI_MODE (used to stop the ring across resets) moved > for Tigerlake. Fixup the new location and include a selftest to verify > the location in the default context image. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 18 +++++-- > drivers/gpu/drm/i915/gt/selftest_lrc.c | 73 ++++++++++++++++++++++++++ > 2 files changed, 88 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index 523de1fd4452..09a12d20987b 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -2935,14 +2935,26 @@ static void reset_csb_pointers(struct intel_engine_cs *engine) > &execlists->csb_status[reset_value]); > } > > +static int lrc_ring_mi_mode(const struct intel_engine_cs *engine) > +{ > + if (INTEL_GEN(engine->i915) >= 12) > + return 0x60; > + else if (INTEL_GEN(engine->i915) >= 9) > + return 0x54; > + else > + return 0x58; > +} where are those defined on spec so I could help on review? anyway, it seems we want now: intel_lrc_reg.h - #define GEN9_CTX_RING_MI_MODE 0x54 > + > static void __execlists_reset_reg_state(const struct intel_context *ce, > const struct intel_engine_cs *engine) > { > u32 *regs = ce->lrc_reg_state; > + int x; > > - if (INTEL_GEN(engine->i915) >= 9) { > - regs[GEN9_CTX_RING_MI_MODE + 1] &= ~STOP_RING; > - regs[GEN9_CTX_RING_MI_MODE + 1] |= STOP_RING << 16; > + x = lrc_ring_mi_mode(engine); > + if (x != -1) { > + regs[x + 1] &= ~STOP_RING; > + regs[x + 1] |= STOP_RING << 16; > } > } > > diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c > index d5d268be554e..46fa17e9ae0b 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c > +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c > @@ -3165,6 +3165,78 @@ static int live_lrc_layout(void *arg) > return err; > } > > +static int find_offset(const u32 *lri, u32 offset) > +{ > + int i; > + > + for (i = 0; i < PAGE_SIZE / sizeof(u32); i++) > + if (lri[i] == offset) > + return i; > + > + return -1; > +} > + > +static int live_lrc_fixed(void *arg) > +{ > + struct intel_gt *gt = arg; > + struct intel_engine_cs *engine; > + enum intel_engine_id id; > + int err; > + > + /* > + * Check the assumed register offsets match the actual locations in > + * the context image. > + */ > + > + err = 0; > + for_each_engine(engine, gt, id) { > + const struct { > + u32 reg; > + u32 offset; > + const char *name; > + } tbl[] = { > + { > + i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)), > + lrc_ring_mi_mode(engine), > + "RING_MI_MODE", > + }, > + { }, > + }, *t; > + u32 *hw; > + > + if (!engine->default_state) > + continue; > + > + hw = i915_gem_object_pin_map(engine->default_state, > + I915_MAP_WB); > + if (IS_ERR(hw)) { > + err = PTR_ERR(hw); > + break; > + } > + hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw); > + > + for (t = tbl; t->name; t++) { > + int dw = find_offset(hw, t->reg); > + > + if (dw != t->offset) { > + pr_err("%s: Offset for %s [0x%x] mismatch, found %x, expected %x\n", > + engine->name, > + t->name, > + t->reg, > + dw, > + t->offset); > + err = -EINVAL; > + } > + } > + > + i915_gem_object_unpin_map(engine->default_state); > + if (err) > + break; > + } > + > + return err; > +} > + > static int __live_lrc_state(struct i915_gem_context *fixme, > struct intel_engine_cs *engine, > struct i915_vma *scratch) > @@ -3437,6 +3509,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915) > { > static const struct i915_subtest tests[] = { > SUBTEST(live_lrc_layout), > + SUBTEST(live_lrc_fixed), > SUBTEST(live_lrc_state), > SUBTEST(live_gpr_clear), > }; > -- > 2.24.0.rc1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 523de1fd4452..09a12d20987b 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2935,14 +2935,26 @@ static void reset_csb_pointers(struct intel_engine_cs *engine) &execlists->csb_status[reset_value]); } +static int lrc_ring_mi_mode(const struct intel_engine_cs *engine) +{ + if (INTEL_GEN(engine->i915) >= 12) + return 0x60; + else if (INTEL_GEN(engine->i915) >= 9) + return 0x54; + else + return 0x58; +} + static void __execlists_reset_reg_state(const struct intel_context *ce, const struct intel_engine_cs *engine) { u32 *regs = ce->lrc_reg_state; + int x; - if (INTEL_GEN(engine->i915) >= 9) { - regs[GEN9_CTX_RING_MI_MODE + 1] &= ~STOP_RING; - regs[GEN9_CTX_RING_MI_MODE + 1] |= STOP_RING << 16; + x = lrc_ring_mi_mode(engine); + if (x != -1) { + regs[x + 1] &= ~STOP_RING; + regs[x + 1] |= STOP_RING << 16; } } diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index d5d268be554e..46fa17e9ae0b 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -3165,6 +3165,78 @@ static int live_lrc_layout(void *arg) return err; } +static int find_offset(const u32 *lri, u32 offset) +{ + int i; + + for (i = 0; i < PAGE_SIZE / sizeof(u32); i++) + if (lri[i] == offset) + return i; + + return -1; +} + +static int live_lrc_fixed(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + int err; + + /* + * Check the assumed register offsets match the actual locations in + * the context image. + */ + + err = 0; + for_each_engine(engine, gt, id) { + const struct { + u32 reg; + u32 offset; + const char *name; + } tbl[] = { + { + i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)), + lrc_ring_mi_mode(engine), + "RING_MI_MODE", + }, + { }, + }, *t; + u32 *hw; + + if (!engine->default_state) + continue; + + hw = i915_gem_object_pin_map(engine->default_state, + I915_MAP_WB); + if (IS_ERR(hw)) { + err = PTR_ERR(hw); + break; + } + hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw); + + for (t = tbl; t->name; t++) { + int dw = find_offset(hw, t->reg); + + if (dw != t->offset) { + pr_err("%s: Offset for %s [0x%x] mismatch, found %x, expected %x\n", + engine->name, + t->name, + t->reg, + dw, + t->offset); + err = -EINVAL; + } + } + + i915_gem_object_unpin_map(engine->default_state); + if (err) + break; + } + + return err; +} + static int __live_lrc_state(struct i915_gem_context *fixme, struct intel_engine_cs *engine, struct i915_vma *scratch) @@ -3437,6 +3509,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915) { static const struct i915_subtest tests[] = { SUBTEST(live_lrc_layout), + SUBTEST(live_lrc_fixed), SUBTEST(live_lrc_state), SUBTEST(live_gpr_clear), };
The location of RING_MI_MODE (used to stop the ring across resets) moved for Tigerlake. Fixup the new location and include a selftest to verify the location in the default context image. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 18 +++++-- drivers/gpu/drm/i915/gt/selftest_lrc.c | 73 ++++++++++++++++++++++++++ 2 files changed, 88 insertions(+), 3 deletions(-)