diff mbox series

[3/7] drm/i915: set num_fence_regs to 0 if there is no aperture

Message ID 20191029095856.25431-3-matthew.auld@intel.com (mailing list archive)
State New, archived
Headers show
Series [1/7] drm/i915: define i915_ggtt_has_aperture | expand

Commit Message

Matthew Auld Oct. 29, 2019, 9:58 a.m. UTC 
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

We can't fence anything without aperture.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Chris Wilson Oct. 29, 2019, 10:06 a.m. UTC | #1 
Quoting Matthew Auld (2019-10-29 09:58:52)
> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> 
> We can't fence anything without aperture.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>

Neat.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
Daniele Ceraolo Spurio Oct. 29, 2019, 9:23 p.m. UTC | #2 
On 10/29/19 2:58 AM, Matthew Auld wrote:
> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> 
> We can't fence anything without aperture.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> index 321189e1b0f2..71efccfde122 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> @@ -846,8 +846,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
>   
>   	detect_bit_6_swizzle(ggtt);
>   
> -	if (INTEL_GEN(i915) >= 7 &&
> -	    !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
> +	if (!i915_ggtt_has_aperture(ggtt))

Daniel had mentioned that the fencing HW has been nerfed in gen12 and 
suggested settings num_fences to zero for all gen12+. Should we go 
directly with that?

Daniele

> +		num_fences = 0;
> +	else if (INTEL_GEN(i915) >= 7 &&
> +		 !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
>   		num_fences = 32;
>   	else if (INTEL_GEN(i915) >= 4 ||
>   		 IS_I945G(i915) || IS_I945GM(i915) ||
>
Chris Wilson Oct. 29, 2019, 9:44 p.m. UTC | #3 
Quoting Daniele Ceraolo Spurio (2019-10-29 21:23:16)
> 
> 
> On 10/29/19 2:58 AM, Matthew Auld wrote:
> > From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > 
> > We can't fence anything without aperture.
> > 
> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 ++++--
> >   1 file changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> > index 321189e1b0f2..71efccfde122 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> > @@ -846,8 +846,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
> >   
> >       detect_bit_6_swizzle(ggtt);
> >   
> > -     if (INTEL_GEN(i915) >= 7 &&
> > -         !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
> > +     if (!i915_ggtt_has_aperture(ggtt))
> 
> Daniel had mentioned that the fencing HW has been nerfed in gen12 and 
> suggested settings num_fences to zero for all gen12+. Should we go 
> directly with that?

Do fences exist, yes/no? If there are literally no fences forevermore...
tgl begs to differ though.
-Chris
Daniele Ceraolo Spurio Oct. 29, 2019, 9:50 p.m. UTC | #4 
On 10/29/19 2:44 PM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2019-10-29 21:23:16)
>>
>>
>> On 10/29/19 2:58 AM, Matthew Auld wrote:
>>> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>>
>>> We can't fence anything without aperture.
>>>
>>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
>>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 ++++--
>>>    1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>>> index 321189e1b0f2..71efccfde122 100644
>>> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>>> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>>> @@ -846,8 +846,10 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
>>>    
>>>        detect_bit_6_swizzle(ggtt);
>>>    
>>> -     if (INTEL_GEN(i915) >= 7 &&
>>> -         !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
>>> +     if (!i915_ggtt_has_aperture(ggtt))
>>
>> Daniel had mentioned that the fencing HW has been nerfed in gen12 and
>> suggested settings num_fences to zero for all gen12+. Should we go
>> directly with that?
> 
> Do fences exist, yes/no? If there are literally no fences forevermore...
> tgl begs to differ though.
> -Chris
> 

The registers are there in the specs and I don't see any special notes 
about their usage. I'll leave it to Daniel to comment on the capability 
reduction he mentioned. Not a blocker for this patch in the meantime.

Daniele
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index 321189e1b0f2..71efccfde122 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -846,8 +846,10 @@  void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
 
 	detect_bit_6_swizzle(ggtt);
 
-	if (INTEL_GEN(i915) >= 7 &&
-	    !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
+	if (!i915_ggtt_has_aperture(ggtt))
+		num_fences = 0;
+	else if (INTEL_GEN(i915) >= 7 &&
+		 !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
 		num_fences = 32;
 	else if (INTEL_GEN(i915) >= 4 ||
 		 IS_I945G(i915) || IS_I945GM(i915) ||