[v4,4/8] dt-bindings: mmc: arasan: Add optional properties for Arasan SDHCI
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Message ID 1572345042-101207-4-git-send-email-manish.narani@xilinx.com
State New
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Series
  • [v4,1/8] mmc: sdhci-of-arasan: Separate out clk related data to another structure
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Commit Message

Manish Narani Oct. 29, 2019, 10:30 a.m. UTC
Add optional properties for Arasan SDHCI which are used to set clk delays
for different speed modes in the controller.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
---
 .../devicetree/bindings/mmc/arasan,sdhci.txt     | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

Comments

Ulf Hansson Oct. 30, 2019, 2:57 p.m. UTC | #1
On Tue, 29 Oct 2019 at 11:30, Manish Narani <manish.narani@xilinx.com> wrote:
>
> Add optional properties for Arasan SDHCI which are used to set clk delays
> for different speed modes in the controller.
>
> Signed-off-by: Manish Narani <manish.narani@xilinx.com>
> ---
>  .../devicetree/bindings/mmc/arasan,sdhci.txt     | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> index b51e40b2e0c5..c0f505b6cab5 100644
> --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> @@ -46,6 +46,22 @@ Optional Properties:
>      properly. Test mode can be used to force the controller to function.
>    - xlnx,int-clock-stable-broken: when present, the controller always reports
>      that the internal clock is stable even when it is not.
> +  - arasan-clk-phase-legacy: Input/Output Clock Delay pair in degrees for Legacy Mode.
> +  - arasan-clk-phase-mmc-hs: Input/Output Clock Delay pair degrees for MMC HS.
> +  - arasan-clk-phase-sd-hs: Input/Output Clock Delay pair in degrees for SD HS.
> +  - arasan-clk-phase-uhs-sdr12: Input/Output Clock Delay pair in degrees for SDR12.
> +  - arasan-clk-phase-uhs-sdr25: Input/Output Clock Delay pair in degrees for SDR25.
> +  - arasan-clk-phase-uhs-sdr50: Input/Output Clock Delay pair in degrees for SDR50.
> +  - arasan-clk-phase-uhs-sdr104: Input/Output Clock Delay pair in degrees for SDR104.
> +  - arasan-clk-phase-uhs-ddr50: Input/Output Clock Delay pair in degrees for SD DDR50.
> +  - arasan-clk-phase-mmc-ddr52: Input/Output Clock Delay pair in degrees for MMC DDR52.
> +  - arasan-clk-phase-mmc-hs200: Input/Output Clock Delay pair in degrees for MMC HS200.
> +  - arasan-clk-phase-mmc-hs400: Input/Output Clock Delay pair in degrees for MMC HS400.

I don't mind if you convert these to common mmc bindings.

I think other controllers/platforms may find them useful, at least at
some point, if not already.

> +
> +  Above mentioned are the clock (phase) delays which are to be configured in the
> +  controller while switching to particular speed mode. The range of values are
> +  0 to 359 degrees. If not specified, driver will configure the default value
> +  defined for particular mode in it.
>
>  Example:
>         sdhci@e0100000 {
> --
> 2.17.1
>

Kind regards
Uffe
Manish Narani Oct. 31, 2019, 8:54 a.m. UTC | #2
Hi Uffe,

Thanks for your comments. Please see below inline.

> -----Original Message-----
> From: Ulf Hansson <ulf.hansson@linaro.org>
> Sent: Wednesday, October 30, 2019 8:27 PM
> To: Manish Narani <MNARANI@xilinx.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Adrian Hunter <adrian.hunter@intel.com>;
> Michal Simek <michals@xilinx.com>; Jolly Shah <JOLLYS@xilinx.com>; Nava
> kishore Manne <navam@xilinx.com>; Rajan Vaja <RAJANV@xilinx.com>;
> linux-mmc@vger.kernel.org; DTML <devicetree@vger.kernel.org>; Linux
> Kernel Mailing List <linux-kernel@vger.kernel.org>; Linux ARM <linux-arm-
> kernel@lists.infradead.org>; git <git@xilinx.com>
> Subject: Re: [PATCH v4 4/8] dt-bindings: mmc: arasan: Add optional
> properties for Arasan SDHCI
> 
> On Tue, 29 Oct 2019 at 11:30, Manish Narani <manish.narani@xilinx.com>
> wrote:
> >
> > Add optional properties for Arasan SDHCI which are used to set clk delays
> > for different speed modes in the controller.
> >
> > Signed-off-by: Manish Narani <manish.narani@xilinx.com>
> > ---
> >  .../devicetree/bindings/mmc/arasan,sdhci.txt     | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> > index b51e40b2e0c5..c0f505b6cab5 100644
> > --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> > +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> > @@ -46,6 +46,22 @@ Optional Properties:
> >      properly. Test mode can be used to force the controller to function.
> >    - xlnx,int-clock-stable-broken: when present, the controller always
> reports
> >      that the internal clock is stable even when it is not.
> > +  - arasan-clk-phase-legacy: Input/Output Clock Delay pair in degrees for
> Legacy Mode.
> > +  - arasan-clk-phase-mmc-hs: Input/Output Clock Delay pair degrees for
> MMC HS.
> > +  - arasan-clk-phase-sd-hs: Input/Output Clock Delay pair in degrees for SD
> HS.
> > +  - arasan-clk-phase-uhs-sdr12: Input/Output Clock Delay pair in degrees
> for SDR12.
> > +  - arasan-clk-phase-uhs-sdr25: Input/Output Clock Delay pair in degrees
> for SDR25.
> > +  - arasan-clk-phase-uhs-sdr50: Input/Output Clock Delay pair in degrees
> for SDR50.
> > +  - arasan-clk-phase-uhs-sdr104: Input/Output Clock Delay pair in degrees
> for SDR104.
> > +  - arasan-clk-phase-uhs-ddr50: Input/Output Clock Delay pair in degrees
> for SD DDR50.
> > +  - arasan-clk-phase-mmc-ddr52: Input/Output Clock Delay pair in degrees
> for MMC DDR52.
> > +  - arasan-clk-phase-mmc-hs200: Input/Output Clock Delay pair in degrees
> for MMC HS200.
> > +  - arasan-clk-phase-mmc-hs400: Input/Output Clock Delay pair in degrees
> for MMC HS400.
> 
> I don't mind if you convert these to common mmc bindings.
> 
> I think other controllers/platforms may find them useful, at least at
> some point, if not already.

That will be a good thing to do indeed. Will send v5 with making these properties as common.

Thanks,
Manish

> 
> > +
> > +  Above mentioned are the clock (phase) delays which are to be
> configured in the
> > +  controller while switching to particular speed mode. The range of values
> are
> > +  0 to 359 degrees. If not specified, driver will configure the default value
> > +  defined for particular mode in it.
> >
> >  Example:
> >         sdhci@e0100000 {
> > --
> > 2.17.1
> >
> 
> Kind regards
> Uffe

Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index b51e40b2e0c5..c0f505b6cab5 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -46,6 +46,22 @@  Optional Properties:
     properly. Test mode can be used to force the controller to function.
   - xlnx,int-clock-stable-broken: when present, the controller always reports
     that the internal clock is stable even when it is not.
+  - arasan-clk-phase-legacy: Input/Output Clock Delay pair in degrees for Legacy Mode.
+  - arasan-clk-phase-mmc-hs: Input/Output Clock Delay pair degrees for MMC HS.
+  - arasan-clk-phase-sd-hs: Input/Output Clock Delay pair in degrees for SD HS.
+  - arasan-clk-phase-uhs-sdr12: Input/Output Clock Delay pair in degrees for SDR12.
+  - arasan-clk-phase-uhs-sdr25: Input/Output Clock Delay pair in degrees for SDR25.
+  - arasan-clk-phase-uhs-sdr50: Input/Output Clock Delay pair in degrees for SDR50.
+  - arasan-clk-phase-uhs-sdr104: Input/Output Clock Delay pair in degrees for SDR104.
+  - arasan-clk-phase-uhs-ddr50: Input/Output Clock Delay pair in degrees for SD DDR50.
+  - arasan-clk-phase-mmc-ddr52: Input/Output Clock Delay pair in degrees for MMC DDR52.
+  - arasan-clk-phase-mmc-hs200: Input/Output Clock Delay pair in degrees for MMC HS200.
+  - arasan-clk-phase-mmc-hs400: Input/Output Clock Delay pair in degrees for MMC HS400.
+
+  Above mentioned are the clock (phase) delays which are to be configured in the
+  controller while switching to particular speed mode. The range of values are
+  0 to 359 degrees. If not specified, driver will configure the default value
+  defined for particular mode in it.
 
 Example:
 	sdhci@e0100000 {