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Tue, 29 Oct 2019 03:30:46 -0700 Received: from [172.23.64.106] (helo=xhdvnc125.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iPOlx-0005kZ-4m; Tue, 29 Oct 2019 03:30:45 -0700 Received: by xhdvnc125.xilinx.com (Postfix, from userid 16987) id 6CEE512175D; Tue, 29 Oct 2019 16:00:44 +0530 (IST) From: Manish Narani To: ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, adrian.hunter@intel.com, michal.simek@xilinx.com, jolly.shah@xilinx.com, nava.manne@xilinx.com, rajan.vaja@xilinx.com, manish.narani@xilinx.com Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, git@xilinx.com Subject: [PATCH v4 4/8] dt-bindings: mmc: arasan: Add optional properties for Arasan SDHCI Date: Tue, 29 Oct 2019 16:00:38 +0530 Message-Id: <1572345042-101207-4-git-send-email-manish.narani@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1572345042-101207-1-git-send-email-manish.narani@xilinx.com> References: <1572345042-101207-1-git-send-email-manish.narani@xilinx.com> X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(39860400002)(136003)(396003)(346002)(376002)(189003)(199004)(336012)(70206006)(5660300002)(81166006)(6266002)(8936002)(16586007)(48376002)(42186006)(4326008)(51416003)(70586007)(50226002)(316002)(107886003)(446003)(47776003)(426003)(356004)(6666004)(50466002)(36386004)(11346002)(126002)(2616005)(476003)(2906002)(103686004)(478600001)(44832011)(106002)(26005)(36756003)(305945005)(486006)(76176011)(186003)(8676002)(81156014);DIR:OUT;SFP:1101;SCL:1;SRVR:CH2PR02MB6168;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c76589f8-1423-4ed2-78e9-08d75c5b12e9 X-MS-TrafficTypeDiagnostic: CH2PR02MB6168: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-Forefront-PRVS: 0205EDCD76 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jeLN0BEX3Xg30taVXUxX3788p/Kx0Z1IAOL8TnD5UJvWJ/egjnXHYHkG0zzm67Vbq1CDTS/rNIN9cGs8TZqOOPk+BrGji1VK71W4vz/txif9oh9+eD9FhXR7as/Ag2/tDsx6l7vVDP4ntSQuE793R71SwmAkpzZ7LE1tjaeaMprvW/mxkRr9LszNsbAKgpMiRzkLorztjzgk72Bsm5ZYd9LxFwpExL5k+XRwtPPgGOZVjxJgu6pLd6AXhBzZbXqbRjHgpqStiAYxaEwqbuqfSsbVl8sxbTaeBGY5532DKP/Gjsn4Sg5b/X9hqnzl/zd+pinLxRA9v9o8eZmREQnLLEhG41SbGYS6kvtkNOF5CobLNJ21QOpNqVxIwuqespG8oMBCq71sdXPYxA/3gZh6PzziiHvUe5Q/2+m1oYnhFTx7ITv1u6ZUkCv0ZJ887c7X X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2019 10:30:52.4153 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c76589f8-1423-4ed2-78e9-08d75c5b12e9 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR02MB6168 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add optional properties for Arasan SDHCI which are used to set clk delays for different speed modes in the controller. Signed-off-by: Manish Narani --- .../devicetree/bindings/mmc/arasan,sdhci.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index b51e40b2e0c5..c0f505b6cab5 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -46,6 +46,22 @@ Optional Properties: properly. Test mode can be used to force the controller to function. - xlnx,int-clock-stable-broken: when present, the controller always reports that the internal clock is stable even when it is not. + - arasan-clk-phase-legacy: Input/Output Clock Delay pair in degrees for Legacy Mode. + - arasan-clk-phase-mmc-hs: Input/Output Clock Delay pair degrees for MMC HS. + - arasan-clk-phase-sd-hs: Input/Output Clock Delay pair in degrees for SD HS. + - arasan-clk-phase-uhs-sdr12: Input/Output Clock Delay pair in degrees for SDR12. + - arasan-clk-phase-uhs-sdr25: Input/Output Clock Delay pair in degrees for SDR25. + - arasan-clk-phase-uhs-sdr50: Input/Output Clock Delay pair in degrees for SDR50. + - arasan-clk-phase-uhs-sdr104: Input/Output Clock Delay pair in degrees for SDR104. + - arasan-clk-phase-uhs-ddr50: Input/Output Clock Delay pair in degrees for SD DDR50. + - arasan-clk-phase-mmc-ddr52: Input/Output Clock Delay pair in degrees for MMC DDR52. + - arasan-clk-phase-mmc-hs200: Input/Output Clock Delay pair in degrees for MMC HS200. + - arasan-clk-phase-mmc-hs400: Input/Output Clock Delay pair in degrees for MMC HS400. + + Above mentioned are the clock (phase) delays which are to be configured in the + controller while switching to particular speed mode. The range of values are + 0 to 359 degrees. If not specified, driver will configure the default value + defined for particular mode in it. Example: sdhci@e0100000 {