[6/7] clk: imx: sccg-pll: Switch to clk_hw based API
diff mbox series

Message ID 1572356175-24950-7-git-send-email-peng.fan@nxp.com
State New
Headers show
Series
  • clk: imx: switch to clk_hw based API
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Commit Message

Peng Fan Oct. 29, 2019, 1:41 p.m. UTC
From: Peng Fan <peng.fan@nxp.com>

Switch the imx_clk_sccg_pll function to clk_hw based API, rename
accordingly and add a macro for clk based legacy. This allows us to
move closer to a clear split between consumer and provider clk APIs.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-sccg-pll.c | 4 ++--
 drivers/clk/imx/clk.h          | 8 ++++++--
 2 files changed, 8 insertions(+), 4 deletions(-)

Patch
diff mbox series

diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c
index 5d65f65c512e..2cf874813458 100644
--- a/drivers/clk/imx/clk-sccg-pll.c
+++ b/drivers/clk/imx/clk-sccg-pll.c
@@ -506,7 +506,7 @@  static const struct clk_ops clk_sccg_pll_ops = {
 	.determine_rate	= clk_sccg_pll_determine_rate,
 };
 
-struct clk *imx_clk_sccg_pll(const char *name,
+struct clk_hw *imx_clk_hw_sccg_pll(const char *name,
 				const char * const *parent_names,
 				u8 num_parents,
 				u8 parent, u8 bypass1, u8 bypass2,
@@ -545,5 +545,5 @@  struct clk *imx_clk_sccg_pll(const char *name,
 		return ERR_PTR(ret);
 	}
 
-	return hw->clk;
+	return hw;
 }
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index a260b8dd3256..9de6bc590638 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -116,13 +116,17 @@  struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
 #define imx_clk_frac_pll(name, parent_name, base) \
 	imx_clk_hw_frac_pll(name, parent_name, base)->clk
 
-struct clk *imx_clk_sccg_pll(const char *name,
+struct clk_hw *imx_clk_hw_sccg_pll(const char *name,
 				const char * const *parent_names,
 				u8 num_parents,
 				u8 parent, u8 bypass1, u8 bypass2,
 				void __iomem *base,
 				unsigned long flags);
-
+#define imx_clk_sccg_pll(name, parent_names, num_parents, parent, \
+			 bypass1, bypass2, base, flags) \
+	imx_clk_hw_sccg_pll(name, parent_names, num_parents, parent, \
+			    bypass1, bypass2, base, flags)->clk
+
 enum imx_pllv3_type {
 	IMX_PLLV3_GENERIC,
 	IMX_PLLV3_SYS,