From patchwork Tue Oct 29 13:52:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lipski, Mikita" X-Patchwork-Id: 11217943 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DF4BE112B for ; Tue, 29 Oct 2019 13:53:10 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C5C4920862 for ; Tue, 29 Oct 2019 13:53:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C5C4920862 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amd.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C47F56E3B2; Tue, 29 Oct 2019 13:52:59 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from NAM05-DM3-obe.outbound.protection.outlook.com (mail-eopbgr730079.outbound.protection.outlook.com [40.107.73.79]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8B3C46E3AC; Tue, 29 Oct 2019 13:52:57 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=fjDoChmcMLkJODWwKvZE6Ze2V5nCw/SPz8f82Fi3AtjfD6KCI7tJxiyqgVbD5xw35bBQpMJ7xlnmV9Yod7iUgxBkIaij4P9KVWPYoz666ap4Wl1WNKZQIDzaDpS6whrX4qUwTT5PtGweISADQGqer40/jJVXD33o7Ype004pSpm5wiSk9Xj7nxysx7RJkC+xyFqO+QLDttqFklECnufjojKX/nciHu4oMmWy32pOVzJYmMVwqjlvqTsCVG2Cgd+kLJHRfDQFRrRFi9zDGL0pqPb5l9xJgOVnTRImlDSgQfbUAdT8PRpJz00Jqq6/2suO7QJOlD1zVd9hWreNyd7t1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jGaKkdX6iXLUfgbzbaOda9nwKh4JkqLVkiRPkrxpr4w=; b=dUhcDys6Q0Y5IcdPCLhz3MuM2bCcUVdZRfv1u2MwdwMNlQtaoUb+ImsVrGuwCUN4vEN2KlqkZB/g6ifCBO1QnrEi6Jws/7jjhtSkANa0cg6UWcdOWPQ9jqlVRR09+WWPHImCmGIqr+aVD2s6bYTce//JOawBDW83KlOVlHwDAsn7H1UWxubvV/8XG01/rhj54dAgR5/qyrho8vh/N3MJBqvhPgNPibv4arzSTKKHawgNif/k3E2/raK1CAWM5lqt6e+odU2ANHq/1aasUkkA6Y0FnfRhHaeyWnKzaF3VB5qTPKByGyctXO1fDQtpBLqApcZZNZqNUknYIa5zYg6D/w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=none (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.freedesktop.org smtp.mailfrom=amd.com; dmarc=permerror action=none header.from=amd.com; dkim=none (message not signed); arc=none Received: from BN8PR12CA0008.namprd12.prod.outlook.com (2603:10b6:408:60::21) by BYAPR12MB3288.namprd12.prod.outlook.com (2603:10b6:a03:130::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2387.23; Tue, 29 Oct 2019 13:52:53 +0000 Received: from CO1NAM03FT040.eop-NAM03.prod.protection.outlook.com (2a01:111:f400:7e48::204) by BN8PR12CA0008.outlook.office365.com (2603:10b6:408:60::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2408.17 via Frontend Transport; Tue, 29 Oct 2019 13:52:53 +0000 Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Received: from SATLEXMB02.amd.com (165.204.84.17) by CO1NAM03FT040.mail.protection.outlook.com (10.152.81.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.2387.20 via Frontend Transport; Tue, 29 Oct 2019 13:52:52 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB02.amd.com (10.181.40.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 29 Oct 2019 08:52:52 -0500 Received: from SATLEXMB01.amd.com (10.181.40.142) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 29 Oct 2019 08:52:51 -0500 Received: from mlipski-pc.amd.com (10.180.168.240) by SATLEXMB01.amd.com (10.181.40.142) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Tue, 29 Oct 2019 08:52:51 -0500 From: To: Subject: [PATCH 02/13] drm/dp_mst: Add PBN calculation for DSC modes Date: Tue, 29 Oct 2019 09:52:34 -0400 Message-ID: <20191029135245.31152-3-mikita.lipski@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191029135245.31152-1-mikita.lipski@amd.com> References: <20191029135245.31152-1-mikita.lipski@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:165.204.84.17; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(396003)(376002)(346002)(136003)(39860400002)(428003)(199004)(189003)(51416003)(6916009)(7696005)(4326008)(2876002)(48376002)(81166006)(81156014)(36756003)(70206006)(70586007)(2906002)(2351001)(26005)(8936002)(53416004)(186003)(8676002)(76176011)(54906003)(47776003)(5660300002)(316002)(478600001)(50226002)(86362001)(1076003)(11346002)(446003)(356004)(16586007)(336012)(2616005)(6666004)(305945005)(486006)(126002)(476003)(50466002)(426003)(16060500001); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR12MB3288; H:SATLEXMB02.amd.com; FPR:; SPF:None; LANG:en; PTR:InfoDomainNonexistent; A:1; MX:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 50922184-7606-4dce-ac9c-08d75c774b4d X-MS-TrafficTypeDiagnostic: BYAPR12MB3288: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-Forefront-PRVS: 0205EDCD76 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: a8FDK6dYpEvrZY7N0C4HVdByNbvWFGCtI6s4XYjrl52KXDCgpfixDd5Cy7jG+r394o7yS4ZKf0KJynCBoiqKKLa327ujn9bNWNtdDAW9RkEWF6qX9PRlIRbWKbeH128WFKh+Jh1I+PnYw5VradPWsn8vW5/3Q0WmKBiq98qgSTzy3PNIbST0Z4e7YvQqNBKU6QiDUqbxZL4SiRA/un+Pd/nOW3Ow7zr6I4mMeOJPzb0VAa6CvQk2FfYwxmd4SDvTnxZhtsK2O3PNppgF/rIqB3XVGEQSrrZpNd+PL2p9nP8Swix6oK7Hvcd66+n6mm5byixfpdJG5Z5t1C5xmvQJODsQ9mPvJZUbqfvk414n5ijP54I4IbqHLtnrL31dQCOTFGCbg7Bx5NASQHsl3X4DU9kaKbffVs11n+A3tjFnLX7DxJeSdvsthKnkC2MA1zGz X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2019 13:52:52.8678 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 50922184-7606-4dce-ac9c-08d75c774b4d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3288 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jGaKkdX6iXLUfgbzbaOda9nwKh4JkqLVkiRPkrxpr4w=; b=zfpbPBKTGJXh9x4i7kJ5HoQajk525QYPVg1NHAowewRJ563MAFWqkV3H4JNqSvqAAf9YW8BhcqOIBnxepqW10YcA/gXvlWgEz2NwhGftSsssV5Ew0LrlyUkkuFtSJ7EQb+Pr4Z3npf2tlYGQ/N4TdDryxIdhWB67I4cyun3JhkM= X-Mailman-Original-Authentication-Results: spf=none (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; lists.freedesktop.org; dkim=none (message not signed) header.d=none;lists.freedesktop.org; dmarc=permerror action=none header.from=amd.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Francis , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: David Francis With DSC, bpp can be fractional in multiples of 1/16. Change drm_dp_calc_pbn_mode to reflect this, adding a new parameter bool dsc. When this parameter is true, treat the bpp parameter as having units not of bits per pixel, but 1/16 of a bit per pixel v2: Don't add separate function for this Reviewed-by: Manasi Navare Reviewed-by: Lyude Paul Reviewed-by: Harry Wentland Signed-off-by: David Francis --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/drm_dp_mst_topology.c | 16 ++++++++++++---- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ++- drivers/gpu/drm/nouveau/dispnv50/disp.c | 3 ++- drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- include/drm/drm_dp_mst_helper.h | 3 +-- 6 files changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 28f6b93ab371..0909ace4f1b4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4633,7 +4633,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, if (!state->duplicated) { bpp = (uint8_t)connector->display_info.bpc * 3; clock = adjusted_mode->clock; - dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp); + dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); } dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state, mst_mgr, diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 82add736e17d..3e7b7553cf4d 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -3534,10 +3534,11 @@ EXPORT_SYMBOL(drm_dp_check_act_status); * drm_dp_calc_pbn_mode() - Calculate the PBN for a mode. * @clock: dot clock for the mode * @bpp: bpp for the mode. + * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel * * This uses the formula in the spec to calculate the PBN value for a mode. */ -int drm_dp_calc_pbn_mode(int clock, int bpp) +int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) { u64 kbps; s64 peak_kbps; @@ -3555,11 +3556,18 @@ int drm_dp_calc_pbn_mode(int clock, int bpp) * peak_kbps *= (1006/1000) * peak_kbps *= (64/54) * peak_kbps *= 8 convert to bytes + * + * If the bpp is in units of 1/16, further divide by 16. Put this + * factor in the numerator rather than the denominator to avoid + * integer overflow */ numerator = 64 * 1006; denominator = 54 * 8 * 1000 * 1000; + if (dsc) + numerator /= 16; + kbps *= numerator; peak_kbps = drm_fixp_from_fraction(kbps, denominator); @@ -3570,19 +3578,19 @@ EXPORT_SYMBOL(drm_dp_calc_pbn_mode); static int test_calc_pbn_mode(void) { int ret; - ret = drm_dp_calc_pbn_mode(154000, 30); + ret = drm_dp_calc_pbn_mode(154000, 30, false); if (ret != 689) { DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, expected PBN %d, actual PBN %d.\n", 154000, 30, 689, ret); return -EINVAL; } - ret = drm_dp_calc_pbn_mode(234000, 30); + ret = drm_dp_calc_pbn_mode(234000, 30, false); if (ret != 1047) { DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, expected PBN %d, actual PBN %d.\n", 234000, 30, 1047, ret); return -EINVAL; } - ret = drm_dp_calc_pbn_mode(297000, 24); + ret = drm_dp_calc_pbn_mode(297000, 24, false); if (ret != 1063) { DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, expected PBN %d, actual PBN %d.\n", 297000, 24, 1063, ret); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 2c5ac3dd647f..dfac450841df 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -61,7 +61,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, crtc_state->pipe_bpp = bpp; crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, - crtc_state->pipe_bpp); + crtc_state->pipe_bpp, + false); slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, port, crtc_state->pbn); diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index f1dbc7852414..c45832230ccc 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -778,7 +778,8 @@ nv50_msto_atomic_check(struct drm_encoder *encoder, if (!state->duplicated) asyh->dp.pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, - connector->display_info.bpc * 3); + connector->display_info.bpc * 3, + false); if (crtc_state->mode_changed) { slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c b/drivers/gpu/drm/radeon/radeon_dp_mst.c index 2994f07fbad9..c997f88218f2 100644 --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c @@ -514,7 +514,7 @@ static bool radeon_mst_mode_fixup(struct drm_encoder *encoder, mst_enc = radeon_encoder->enc_priv; - mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp); + mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp, false); mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices; DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index 2ba6253ea6d3..9116b2c95239 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -610,8 +610,7 @@ bool drm_dp_mst_port_has_audio(struct drm_dp_mst_topology_mgr *mgr, struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port); -int drm_dp_calc_pbn_mode(int clock, int bpp); - +int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc); bool drm_dp_mst_allocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int pbn, int slots);