[1/2] arm: dts: imx7s: ccm: add assigned-clocks
diff mbox series

Message ID 1572515888-3385-2-git-send-email-peng.fan@nxp.com
State New
Headers show
Series
  • clk: imx: imx7d: move setting clk parent to dts
Related show

Commit Message

Peng Fan Oct. 31, 2019, 10:01 a.m. UTC
From: Peng Fan <peng.fan@nxp.com>

Add assigned-clocks and assigned-clock-parents, then
we could remove the clk_set_parent code in clk-imx7d.c.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/boot/dts/imx7s.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Comments

Fabio Estevam Oct. 31, 2019, 12:09 p.m. UTC | #1
Hi Peng,

On Thu, Oct 31, 2019 at 7:01 AM Peng Fan <peng.fan@nxp.com> wrote:
>
> From: Peng Fan <peng.fan@nxp.com>
>
> Add assigned-clocks and assigned-clock-parents, then
> we could remove the clk_set_parent code in clk-imx7d.c.

Change itself looks good, but please do not mention the clock driver
in the commit log.

Devicetree should be OS agnostic.

Patch
diff mbox series

diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 1b812f4e7453..36ae864d9b7c 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -625,6 +625,26 @@ 
 				#clock-cells = <1>;
 				clocks = <&ckil>, <&osc>;
 				clock-names = "ckil", "osc";
+				/*
+				 * gpt1 root clk must be twice as gpt
+				 * counter freq
+				 */
+				assigned-clocks = <&clks IMX7D_PLL_ARM_MAIN_BYPASS>,
+						<&clks IMX7D_PLL_DRAM_MAIN_BYPASS>,
+						<&clks IMX7D_PLL_SYS_MAIN_BYPASS>,
+						<&clks IMX7D_PLL_ENET_MAIN_BYPASS>,
+						<&clks IMX7D_PLL_AUDIO_MAIN_BYPASS>,
+						<&clks IMX7D_PLL_VIDEO_MAIN_BYPASS>,
+						<&clks IMX7D_MIPI_CSI_ROOT_SRC>,
+						<&clks IMX7D_GPT1_ROOT_SRC>;
+				assigned-clock-parents = <&clks IMX7D_PLL_ARM_MAIN>,
+							 <&clks IMX7D_PLL_DRAM_MAIN>,
+							 <&clks IMX7D_PLL_SYS_MAIN>,
+							 <&clks IMX7D_PLL_ENET_MAIN>,
+							 <&clks IMX7D_PLL_AUDIO_MAIN>,
+							 <&clks IMX7D_PLL_VIDEO_MAIN>,
+							 <&clks IMX7D_PLL_SYS_PFD3_CLK>,
+							 <&clks IMX7D_OSC_24M_CLK>;
 			};
 
 			src: src@30390000 {