clk: zynqmp: Add support for custom type flags
diff mbox series

Message ID 1573117086-7405-1-git-send-email-rajan.vaja@xilinx.com
State New
Headers show
Series
  • clk: zynqmp: Add support for custom type flags
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Commit Message

Rajan Vaja Nov. 7, 2019, 8:58 a.m. UTC
Store extra custom type flags received from firmware.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 drivers/clk/zynqmp/clkc.c    | 8 +++++++-
 drivers/clk/zynqmp/divider.c | 4 ++--
 2 files changed, 9 insertions(+), 3 deletions(-)

Comments

Michael Tretter Nov. 7, 2019, 4:49 p.m. UTC | #1
On Thu, 07 Nov 2019 00:58:06 -0800, Rajan Vaja wrote:
> Store extra custom type flags received from firmware.
> 
> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>  drivers/clk/zynqmp/clkc.c    | 8 +++++++-
>  drivers/clk/zynqmp/divider.c | 4 ++--
>  2 files changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
> index a11f93e..0dea55e 100644
> --- a/drivers/clk/zynqmp/clkc.c
> +++ b/drivers/clk/zynqmp/clkc.c
> @@ -2,7 +2,7 @@
>  /*
>   * Zynq UltraScale+ MPSoC clock controller
>   *
> - *  Copyright (C) 2016-2018 Xilinx
> + *  Copyright (C) 2016-2019 Xilinx
>   *
>   * Based on drivers/clk/zynq/clkc.c
>   */
> @@ -86,6 +86,8 @@ struct topology_resp {
>  #define CLK_TOPOLOGY_TYPE		GENMASK(3, 0)
>  #define CLK_TOPOLOGY_FLAGS		GENMASK(23, 8)
>  #define CLK_TOPOLOGY_TYPE_FLAGS		GENMASK(31, 24)
> +#define CLK_TOPOLOGY_TYPE_FLAG2		GENMASK(7, 4)

What kind of function do these flags indicate? The name is really not
obvious to me.

I would prefer if the defines are kept in the order of the bits in the
field, i.e., the new define should go between CLK_TOPOLOGY_TYPE and
CLK_TOPOLOGY_FLAGS.

> +#define CLK_TOPOLOGY_TYPE_FLAG_BITS	8
>  	u32 topology[CLK_GET_TOPOLOGY_RESP_WORDS];
>  };
>  
> @@ -396,6 +398,10 @@ static int __zynqmp_clock_get_topology(struct clock_topology *topology,
>  		topology[*nnodes].type_flag =
>  				FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS,
>  					  response->topology[i]);
> +		topology[*nnodes].type_flag |=
> +			FIELD_GET(CLK_TOPOLOGY_TYPE_FLAG2,
> +				  response->topology[i]) <<
> +			CLK_TOPOLOGY_TYPE_FLAG_BITS;

Shifting the new flags into the existing type_flag field seems like a
source for code that is really difficult to read. Maybe use a new field
in the topology for the new flags with a proper name?

>  		(*nnodes)++;
>  	}
>  
> diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
> index d8f5b70d..d376529 100644
> --- a/drivers/clk/zynqmp/divider.c
> +++ b/drivers/clk/zynqmp/divider.c
> @@ -2,7 +2,7 @@
>  /*
>   * Zynq UltraScale+ MPSoC Divider support
>   *
> - *  Copyright (C) 2016-2018 Xilinx
> + *  Copyright (C) 2016-2019 Xilinx
>   *
>   * Adjustable divider clock implementation
>   */
> @@ -37,7 +37,7 @@
>   */
>  struct zynqmp_clk_divider {
>  	struct clk_hw hw;
> -	u8 flags;
> +	u16 flags;

This change looks unrelated to the remaining patch.

Michael

>  	bool is_frac;
>  	u32 clk_id;
>  	u32 div_type;
Rajan Vaja Nov. 11, 2019, 12:42 p.m. UTC | #2
Hi Michael,

Thanks for the review.

> -----Original Message-----
> From: Michael Tretter <m.tretter@pengutronix.de>
> Sent: 07 November 2019 08:49
> To: Rajan Vaja <RAJANV@xilinx.com>
> Cc: mturquette@baylibre.com; sboyd@kernel.org; Michal Simek
> <michals@xilinx.com>; Jolly Shah <JOLLYS@xilinx.com>;
> dan.carpenter@oracle.com; gustavo@embeddedor.com; linux-
> clk@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; kernel@pengutronix.de
> Subject: Re: [PATCH] clk: zynqmp: Add support for custom type flags
> 
> EXTERNAL EMAIL
> 
> On Thu, 07 Nov 2019 00:58:06 -0800, Rajan Vaja wrote:
> > Store extra custom type flags received from firmware.
> >
> > Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
> > Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
> > Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> > ---
> >  drivers/clk/zynqmp/clkc.c    | 8 +++++++-
> >  drivers/clk/zynqmp/divider.c | 4 ++--
> >  2 files changed, 9 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
> > index a11f93e..0dea55e 100644
> > --- a/drivers/clk/zynqmp/clkc.c
> > +++ b/drivers/clk/zynqmp/clkc.c
> > @@ -2,7 +2,7 @@
> >  /*
> >   * Zynq UltraScale+ MPSoC clock controller
> >   *
> > - *  Copyright (C) 2016-2018 Xilinx
> > + *  Copyright (C) 2016-2019 Xilinx
> >   *
> >   * Based on drivers/clk/zynq/clkc.c
> >   */
> > @@ -86,6 +86,8 @@ struct topology_resp {
> >  #define CLK_TOPOLOGY_TYPE            GENMASK(3, 0)
> >  #define CLK_TOPOLOGY_FLAGS           GENMASK(23, 8)
> >  #define CLK_TOPOLOGY_TYPE_FLAGS              GENMASK(31, 24)
> > +#define CLK_TOPOLOGY_TYPE_FLAG2              GENMASK(7, 4)
> 
> What kind of function do these flags indicate? The name is really not
> obvious to me.
> 
> I would prefer if the defines are kept in the order of the bits in the
> field, i.e., the new define should go between CLK_TOPOLOGY_TYPE and
> CLK_TOPOLOGY_FLAGS.
[Rajan] Ok I will change this in next version.

> 
> > +#define CLK_TOPOLOGY_TYPE_FLAG_BITS  8
> >       u32 topology[CLK_GET_TOPOLOGY_RESP_WORDS];
> >  };
> >
> > @@ -396,6 +398,10 @@ static int __zynqmp_clock_get_topology(struct
> clock_topology *topology,
> >               topology[*nnodes].type_flag =
> >                               FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS,
> >                                         response->topology[i]);
> > +             topology[*nnodes].type_flag |=
> > +                     FIELD_GET(CLK_TOPOLOGY_TYPE_FLAG2,
> > +                               response->topology[i]) <<
> > +                     CLK_TOPOLOGY_TYPE_FLAG_BITS;
> 
> Shifting the new flags into the existing type_flag field seems like a
> source for code that is really difficult to read. Maybe use a new field
> in the topology for the new flags with a proper name?
[Rajan] Will do it in next version.

> 
> >               (*nnodes)++;
> >       }
> >
> > diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
> > index d8f5b70d..d376529 100644
> > --- a/drivers/clk/zynqmp/divider.c
> > +++ b/drivers/clk/zynqmp/divider.c
> > @@ -2,7 +2,7 @@
> >  /*
> >   * Zynq UltraScale+ MPSoC Divider support
> >   *
> > - *  Copyright (C) 2016-2018 Xilinx
> > + *  Copyright (C) 2016-2019 Xilinx
> >   *
> >   * Adjustable divider clock implementation
> >   */
> > @@ -37,7 +37,7 @@
> >   */
> >  struct zynqmp_clk_divider {
> >       struct clk_hw hw;
> > -     u8 flags;
> > +     u16 flags;
> 
> This change looks unrelated to the remaining patch.
[Rajan] Flag width was changed to accommodate custom flags. So needed to change it to u16.
But as you suggested in above comment, will use new variable for custom flag, and so this change won't
Be required.

Thanks,
Rajan
> 
> Michael
> 
> >       bool is_frac;
> >       u32 clk_id;
> >       u32 div_type;

Patch
diff mbox series

diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
index a11f93e..0dea55e 100644
--- a/drivers/clk/zynqmp/clkc.c
+++ b/drivers/clk/zynqmp/clkc.c
@@ -2,7 +2,7 @@ 
 /*
  * Zynq UltraScale+ MPSoC clock controller
  *
- *  Copyright (C) 2016-2018 Xilinx
+ *  Copyright (C) 2016-2019 Xilinx
  *
  * Based on drivers/clk/zynq/clkc.c
  */
@@ -86,6 +86,8 @@  struct topology_resp {
 #define CLK_TOPOLOGY_TYPE		GENMASK(3, 0)
 #define CLK_TOPOLOGY_FLAGS		GENMASK(23, 8)
 #define CLK_TOPOLOGY_TYPE_FLAGS		GENMASK(31, 24)
+#define CLK_TOPOLOGY_TYPE_FLAG2		GENMASK(7, 4)
+#define CLK_TOPOLOGY_TYPE_FLAG_BITS	8
 	u32 topology[CLK_GET_TOPOLOGY_RESP_WORDS];
 };
 
@@ -396,6 +398,10 @@  static int __zynqmp_clock_get_topology(struct clock_topology *topology,
 		topology[*nnodes].type_flag =
 				FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS,
 					  response->topology[i]);
+		topology[*nnodes].type_flag |=
+			FIELD_GET(CLK_TOPOLOGY_TYPE_FLAG2,
+				  response->topology[i]) <<
+			CLK_TOPOLOGY_TYPE_FLAG_BITS;
 		(*nnodes)++;
 	}
 
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index d8f5b70d..d376529 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -2,7 +2,7 @@ 
 /*
  * Zynq UltraScale+ MPSoC Divider support
  *
- *  Copyright (C) 2016-2018 Xilinx
+ *  Copyright (C) 2016-2019 Xilinx
  *
  * Adjustable divider clock implementation
  */
@@ -37,7 +37,7 @@ 
  */
 struct zynqmp_clk_divider {
 	struct clk_hw hw;
-	u8 flags;
+	u16 flags;
 	bool is_frac;
 	u32 clk_id;
 	u32 div_type;