From patchwork Thu Nov 7 15:17:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11233173 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 637BE112B for ; Thu, 7 Nov 2019 15:18:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4C0E32085B for ; Thu, 7 Nov 2019 15:18:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4C0E32085B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 032946F6E8; Thu, 7 Nov 2019 15:17:59 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4AE2D6F6E6; Thu, 7 Nov 2019 15:17:57 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Nov 2019 07:17:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,278,1569308400"; d="scan'208";a="196583777" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga008.jf.intel.com with SMTP; 07 Nov 2019 07:17:54 -0800 Received: by stinkbox (sSMTP sendmail emulation); Thu, 07 Nov 2019 17:17:53 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 07/12] drm/i915: s/blob_data/lut/ Date: Thu, 7 Nov 2019 17:17:20 +0200 Message-Id: <20191107151725.10507-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191107151725.10507-1-ville.syrjala@linux.intel.com> References: <20191107151725.10507-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Swati Sharma , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Ville Syrjälä We're talking about LUT contents here so let's call the thing 'lut' rather than 'blob_data'. This is the name the load_lut() code used before already. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 66 +++++++++++----------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 5890e3896f8d..43435ed343f2 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1662,7 +1662,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; struct drm_property_blob *blob; - struct drm_color_lut *blob_data; + struct drm_color_lut *lut; u32 i, val; blob = drm_property_create_blob(&dev_priv->drm, @@ -1671,16 +1671,16 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state) if (IS_ERR(blob)) return NULL; - blob_data = blob->data; + lut = blob->data; for (i = 0; i < LEGACY_LUT_LENGTH; i++) { val = I915_READ(PALETTE(pipe, i)); - blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET( + lut[i].red = intel_color_lut_pack(REG_FIELD_GET( LGC_PALETTE_RED_MASK, val), 8); - blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET( + lut[i].green = intel_color_lut_pack(REG_FIELD_GET( LGC_PALETTE_GREEN_MASK, val), 8); - blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET( + lut[i].blue = intel_color_lut_pack(REG_FIELD_GET( LGC_PALETTE_BLUE_MASK, val), 8); } @@ -1703,7 +1703,7 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state) u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; enum pipe pipe = crtc->pipe; struct drm_property_blob *blob; - struct drm_color_lut *blob_data; + struct drm_color_lut *lut; u32 i, val1, val2; blob = drm_property_create_blob(&dev_priv->drm, @@ -1712,25 +1712,25 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state) if (IS_ERR(blob)) return NULL; - blob_data = blob->data; + lut = blob->data; for (i = 0; i < lut_size - 1; i++) { val1 = I915_READ(PALETTE(pipe, 2 * i + 0)); val2 = I915_READ(PALETTE(pipe, 2 * i + 1)); - blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 | + lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 | REG_FIELD_GET(PALETTE_RED_MASK, val1); - blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 | + lut[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 | REG_FIELD_GET(PALETTE_GREEN_MASK, val1); - blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 | + lut[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 | REG_FIELD_GET(PALETTE_BLUE_MASK, val1); } - blob_data[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK, + lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK, I915_READ(PIPEGCMAX(pipe, 0))); - blob_data[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK, + lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK, I915_READ(PIPEGCMAX(pipe, 1))); - blob_data[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK, + lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK, I915_READ(PIPEGCMAX(pipe, 2))); return blob; @@ -1755,7 +1755,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state) u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; enum pipe pipe = crtc->pipe; struct drm_property_blob *blob; - struct drm_color_lut *blob_data; + struct drm_color_lut *lut; u32 i, val; blob = drm_property_create_blob(&dev_priv->drm, @@ -1764,17 +1764,17 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state) if (IS_ERR(blob)) return NULL; - blob_data = blob->data; + lut = blob->data; for (i = 0; i < lut_size; i++) { val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0)); - blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET( + lut[i].green = intel_color_lut_pack(REG_FIELD_GET( CGM_PIPE_GAMMA_GREEN_MASK, val), 10); - blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET( + lut[i].blue = intel_color_lut_pack(REG_FIELD_GET( CGM_PIPE_GAMMA_BLUE_MASK, val), 10); val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1)); - blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET( + lut[i].red = intel_color_lut_pack(REG_FIELD_GET( CGM_PIPE_GAMMA_RED_MASK, val), 10); } @@ -1796,7 +1796,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; struct drm_property_blob *blob; - struct drm_color_lut *blob_data; + struct drm_color_lut *lut; u32 i, val; blob = drm_property_create_blob(&dev_priv->drm, @@ -1805,16 +1805,16 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state) if (IS_ERR(blob)) return NULL; - blob_data = blob->data; + lut = blob->data; for (i = 0; i < LEGACY_LUT_LENGTH; i++) { val = I915_READ(LGC_PALETTE(pipe, i)); - blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET( + lut[i].red = intel_color_lut_pack(REG_FIELD_GET( LGC_PALETTE_RED_MASK, val), 8); - blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET( + lut[i].green = intel_color_lut_pack(REG_FIELD_GET( LGC_PALETTE_GREEN_MASK, val), 8); - blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET( + lut[i].blue = intel_color_lut_pack(REG_FIELD_GET( LGC_PALETTE_BLUE_MASK, val), 8); } @@ -1829,7 +1829,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state) u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; enum pipe pipe = crtc->pipe; struct drm_property_blob *blob; - struct drm_color_lut *blob_data; + struct drm_color_lut *lut; u32 i, val; blob = drm_property_create_blob(&dev_priv->drm, @@ -1838,16 +1838,16 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state) if (IS_ERR(blob)) return NULL; - blob_data = blob->data; + lut = blob->data; for (i = 0; i < lut_size; i++) { val = I915_READ(PREC_PALETTE(pipe, i)); - blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET( + lut[i].red = intel_color_lut_pack(REG_FIELD_GET( PREC_PALETTE_RED_MASK, val), 10); - blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET( + lut[i].green = intel_color_lut_pack(REG_FIELD_GET( PREC_PALETTE_GREEN_MASK, val), 10); - blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET( + lut[i].blue = intel_color_lut_pack(REG_FIELD_GET( PREC_PALETTE_BLUE_MASK, val), 10); } @@ -1876,7 +1876,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index) int hw_lut_size = ivb_lut_10_size(prec_index); enum pipe pipe = crtc->pipe; struct drm_property_blob *blob; - struct drm_color_lut *blob_data; + struct drm_color_lut *lut; u32 i, val; blob = drm_property_create_blob(&dev_priv->drm, @@ -1885,7 +1885,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index) if (IS_ERR(blob)) return NULL; - blob_data = blob->data; + lut = blob->data; I915_WRITE(PREC_PAL_INDEX(pipe), prec_index | PAL_PREC_AUTO_INCREMENT); @@ -1893,11 +1893,11 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index) for (i = 0; i < hw_lut_size; i++) { val = I915_READ(PREC_PAL_DATA(pipe)); - blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET( + lut[i].red = intel_color_lut_pack(REG_FIELD_GET( PREC_PAL_DATA_RED_MASK, val), 10); - blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET( + lut[i].green = intel_color_lut_pack(REG_FIELD_GET( PREC_PAL_DATA_GREEN_MASK, val), 10); - blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET( + lut[i].blue = intel_color_lut_pack(REG_FIELD_GET( PREC_PAL_DATA_BLUE_MASK, val), 10); }