[11/12] drm/i915: Fix readout of PIPEGCMAX
diff mbox series

Message ID 20191107151725.10507-12-ville.syrjala@linux.intel.com
State New
Headers show
Series
  • drm/i915: Gamma cleanups
Related show

Commit Message

Ville Syrjälä Nov. 7, 2019, 3:17 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

PIPEGCMAX is a 11.6 (or 1.16 if you will) value. Ie. it can
represent a value of 1.0 when the maximum we can store in the
software LUT is 0.ffff. Clamp the value so that it gets
saturated to the max the uapi supports.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h            | 1 -
 2 files changed, 2 insertions(+), 2 deletions(-)

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 4b2bd5ac0e8d..3fd517fa1de5 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -422,7 +422,8 @@  static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
 
 static u16 i965_lut_11p6_max_pack(u32 val)
 {
-	return REG_FIELD_GET(PIPEGCMAX_RGB_MASK, val);
+	/* PIPEGCMAX is 11.6, clamp to 10.6 */
+	return clamp_val(val, 0, 0xffff);
 }
 
 static u32 ilk_lut_10(const struct drm_color_lut *color)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a607ea520829..4a8021a33b64 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5871,7 +5871,6 @@  enum {
 
 #define  _PIPEAGCMAX           0x70010
 #define  _PIPEBGCMAX           0x71010
-#define PIPEGCMAX_RGB_MASK     REG_GENMASK(15, 0)
 #define PIPEGCMAX(pipe, i)     _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
 
 #define _PIPE_MISC_A			0x70030