From patchwork Fri Nov 8 10:59:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 11234579 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E64CD1850 for ; Fri, 8 Nov 2019 11:01:23 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C4F35206BA for ; Fri, 8 Nov 2019 11:01:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="bDvOgVHE" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C4F35206BA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NS2pUfEu5zAziJhmKVKFZkCan/I5N/oyXWuyuAcvFMU=; b=bDvOgVHEr7Lmsk omo+MAfVQid/T7Kn0h0YcY/RZAFRRFQToyj3x72cRfRR4UHLfdYCi/U5tN6NsL7VUr4L0g7iNEjfY QgyOfzCxnl7+5lmQu9/184UUMspcHDufLHLpfjqcKOik81JPj6t8huxPjF1lNO8cDzs5H82ZoerU6 KwtIEjePJwsF4Q9lcHH9gl3lhV+Q9jx1lB4du5qLDOFclk5uHMpLMYix9QAJ8PeM67s1MXYN1fdaM vNDDeESkwDRtQJE3o9SzRj0L1YW92jJ6GrgJ7ItXjjjquG/OUR/LEvQHl452f3v1Q6k0WQIZ/AG7B irL/yzq8jUYlSIhF65nQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iT210-0008DK-78; Fri, 08 Nov 2019 11:01:18 +0000 Received: from relay4-d.mail.gandi.net ([217.70.183.196]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iT1zL-0005Fj-BK for linux-arm-kernel@lists.infradead.org; Fri, 08 Nov 2019 10:59:40 +0000 X-Originating-IP: 86.206.246.123 Received: from localhost.localdomain (lfbn-tou-1-421-123.w86-206.abo.wanadoo.fr [86.206.246.123]) (Authenticated sender: miquel.raynal@bootlin.com) by relay4-d.mail.gandi.net (Postfix) with ESMTPSA id 3B8F2E001A; Fri, 8 Nov 2019 10:59:26 +0000 (UTC) From: Miquel Raynal To: Mark Brown , Michal Simek , Naga Sureshkumar Relli Subject: [PATCH 3/7] spi: zynq-qspi: Keep the bitfields naming consistent Date: Fri, 8 Nov 2019 11:59:16 +0100 Message-Id: <20191108105920.19014-4-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191108105920.19014-1-miquel.raynal@bootlin.com> References: <20191108105920.19014-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191108_025935_557122_4FD4CCD1 X-CRM114-Status: GOOD ( 10.67 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [217.70.183.196 listed in wl.mailspike.net] -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [217.70.183.196 listed in list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Miquel Raynal , Tudor Ambarus , linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , linux-spi@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Most of the bits/bitfields #define'd in this driver are composed with: 1/ the driver prefix 2/ the name of the register they apply to Keep the naming consistent by applying this rule to the CONFIG register internals. These definitions will be used in a following change set. Signed-off-by: Miquel Raynal --- drivers/spi/spi-zynq-qspi.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c index 399c3ca33abb..11a484aa3186 100644 --- a/drivers/spi/spi-zynq-qspi.c +++ b/drivers/spi/spi-zynq-qspi.c @@ -61,9 +61,9 @@ * These are the values used in the calculation of baud rate divisor and * setting the slave select. */ -#define ZYNQ_QSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */ -#define ZYNQ_QSPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */ -#define ZYNQ_QSPI_SS_SHIFT 10 /* Slave Select field shift in CR */ +#define ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */ +#define ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift */ +#define ZYNQ_QSPI_CONFIG_PCS 10 /* Peripheral Chip Select */ /* * QSPI Interrupt Registers bit Masks @@ -318,7 +318,7 @@ static void zynq_qspi_chipselect(struct spi_device *spi, bool assert) /* Select the slave */ config_reg &= ~ZYNQ_QSPI_CONFIG_SSCTRL_MASK; config_reg |= (((~(BIT(spi->chip_select))) << - ZYNQ_QSPI_SS_SHIFT) & + ZYNQ_QSPI_CONFIG_PCS) & ZYNQ_QSPI_CONFIG_SSCTRL_MASK); } else { config_reg |= ZYNQ_QSPI_CONFIG_SSCTRL_MASK; @@ -349,7 +349,7 @@ static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi) u32 config_reg, baud_rate_val = 0; /* Set the clock frequency */ - while ((baud_rate_val < ZYNQ_QSPI_BAUD_DIV_MAX) && + while ((baud_rate_val < ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX) && (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) > spi->max_speed_hz) baud_rate_val++; @@ -364,7 +364,7 @@ static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi) config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK; config_reg &= ~ZYNQ_QSPI_CONFIG_BDRATE_MASK; - config_reg |= (baud_rate_val << ZYNQ_QSPI_BAUD_DIV_SHIFT); + config_reg |= (baud_rate_val << ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT); zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg); return 0;