[10/25] drm/i915/execlists: Reduce barrier on context switch to a wmb()
diff mbox series

Message ID 20191110185806.17413-10-chris@chris-wilson.co.uk
State New
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Series
  • [01/25] drm/i915: Protect context while grabbing its name for the request
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Commit Message

Chris Wilson Nov. 10, 2019, 6:57 p.m. UTC
Having been forced to reduce Braswell back to using the aliasing ppgtt,
the coherency issue we previously observed cannot impact us. Reduce the
performance penalty imposed on all platforms from using the mfence to a
mere sfence.

References: cf66b8a0ba14 ("drm/i915/execlists: Apply a full mb before execution for Braswell")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

Comments

Joonas Lahtinen Nov. 11, 2019, 1:19 p.m. UTC | #1
Quoting Chris Wilson (2019-11-10 20:57:51)
> Having been forced to reduce Braswell back to using the aliasing ppgtt,
> the coherency issue we previously observed cannot impact us. Reduce the
> performance penalty imposed on all platforms from using the mfence to a
> mere sfence.
> 
> References: cf66b8a0ba14 ("drm/i915/execlists: Apply a full mb before execution for Braswell")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a06074a26fb5..4b6d9e6b1bfd 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1218,13 +1218,8 @@  static u64 execlists_update_context(const struct i915_request *rq)
 	 * may not be visible to the HW prior to the completion of the UC
 	 * register write and that we may begin execution from the context
 	 * before its image is complete leading to invalid PD chasing.
-	 *
-	 * Furthermore, Braswell, at least, wants a full mb to be sure that
-	 * the writes are coherent in memory (visible to the GPU) prior to
-	 * execution, and not just visible to other CPUs (as is the result of
-	 * wmb).
 	 */
-	mb();
+	wmb();
 
 	desc = ce->lrc_desc;
 	ce->lrc_desc &= ~CTX_DESC_FORCE_RESTORE;