[kvm-unit-tests,v2,1/3] s390x: Fix initial cr0 load comments
diff mbox series

Message ID 20191111153345.22505-2-frankja@linux.ibm.com
State New
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Series
  • s390x: Improve architectural compliance for diag308
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Commit Message

Janosch Frank Nov. 11, 2019, 3:33 p.m. UTC
We need to load cr0 to have access to all fprs during save and restore
of fprs. Saving conditionally on basis of the CR0 AFP bit would be a
pain.

Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
---
 s390x/cstart64.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Thomas Huth Nov. 12, 2019, 9:25 a.m. UTC | #1
On 11/11/2019 16.33, Janosch Frank wrote:
> We need to load cr0 to have access to all fprs during save and restore
> of fprs. Saving conditionally on basis of the CR0 AFP bit would be a
> pain.
> 
> Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
> ---
>  s390x/cstart64.S | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/s390x/cstart64.S b/s390x/cstart64.S
> index 8e2b21e..043e34a 100644
> --- a/s390x/cstart64.S
> +++ b/s390x/cstart64.S
> @@ -94,7 +94,7 @@ memsetxc:
>  	stmg	%r0, %r15, GEN_LC_SW_INT_GRS
>  	/* save cr0 */
>  	stctg	%c0, %c0, GEN_LC_SW_INT_CR0
> -	/* load initial cr0 again */
> +	/* load a cr0 that has the AFP control bit which enables all FPRs */
>  	larl	%r1, initial_cr0
>  	lctlg	%c0, %c0, 0(%r1)
>  	/* save fprs 0-15 + fpc */
> @@ -139,7 +139,7 @@ diag308_load_reset:
>  	xgr	%r2, %r2
>  	br	%r14
>  	/* Success path */
> -	/* We lost cr0 due to the reset */
> +	/* load a cr0 that has the AFP control bit which enables all FPRs */
>  0:	larl	%r1, initial_cr0
>  	lctlg	%c0, %c0, 0(%r1)
>  	RESTORE_REGS
> 

Reviewed-by: Thomas Huth <thuth@redhat.com>

Patch
diff mbox series

diff --git a/s390x/cstart64.S b/s390x/cstart64.S
index 8e2b21e..043e34a 100644
--- a/s390x/cstart64.S
+++ b/s390x/cstart64.S
@@ -94,7 +94,7 @@  memsetxc:
 	stmg	%r0, %r15, GEN_LC_SW_INT_GRS
 	/* save cr0 */
 	stctg	%c0, %c0, GEN_LC_SW_INT_CR0
-	/* load initial cr0 again */
+	/* load a cr0 that has the AFP control bit which enables all FPRs */
 	larl	%r1, initial_cr0
 	lctlg	%c0, %c0, 0(%r1)
 	/* save fprs 0-15 + fpc */
@@ -139,7 +139,7 @@  diag308_load_reset:
 	xgr	%r2, %r2
 	br	%r14
 	/* Success path */
-	/* We lost cr0 due to the reset */
+	/* load a cr0 that has the AFP control bit which enables all FPRs */
 0:	larl	%r1, initial_cr0
 	lctlg	%c0, %c0, 0(%r1)
 	RESTORE_REGS