[15/27] drm/i915/gt: Expose engine->mmio_base via sysfs
diff mbox series

Message ID 20191112092854.869-15-chris@chris-wilson.co.uk
State New
Headers show
Series
  • [01/27] drm/i915: Flush context free work on cleanup
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Commit Message

Chris Wilson Nov. 12, 2019, 9:28 a.m. UTC
Use the per-engine sysfs directory to let userspace discover the
mmio_base of each engine. Prior to recent generations, the user
accessible registers on each engine are at a fixed offset relative to
each engine -- but require absolute addressing. As the absolute address
depends on the actual physical engine, this is not always possible to
determine from userspace (for example icl may expose vcs1 or vcs2 as the
second vcs engine). Make this easy for userspace to discover by
providing the mmio_base in sysfs.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Lionel Landwerlin Nov. 21, 2019, 1:18 p.m. UTC | #1
On 12/11/2019 11:28, Chris Wilson wrote:
> Use the per-engine sysfs directory to let userspace discover the
> mmio_base of each engine. Prior to recent generations, the user
> accessible registers on each engine are at a fixed offset relative to
> each engine -- but require absolute addressing. As the absolute address
> depends on the actual physical engine, this is not always possible to
> determine from userspace (for example icl may expose vcs1 or vcs2 as the
> second vcs engine). Make this easy for userspace to discover by
> providing the mmio_base in sysfs.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>


Sounds like a good idea :


Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>


I guess this being under unstable make this unsuitable to expose through 
i915_query?


-Lionel


> ---
>   drivers/gpu/drm/i915/gt/intel_engine_sysfs.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
> index df263af3a9ea..abddd8d0f9ae 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
> @@ -48,6 +48,15 @@ inst_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
>   static struct kobj_attribute inst_attr =
>   __ATTR(instance, 0444, inst_show, NULL);
>   
> +static ssize_t
> +mmio_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
> +{
> +	return sprintf(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base);
> +}
> +
> +static struct kobj_attribute mmio_attr =
> +__ATTR(mmio_base, 0444, mmio_show, NULL);
> +
>   static const char * const vcs_caps[] = {
>   	[ilog2(I915_VIDEO_CLASS_CAPABILITY_HEVC)] = "hevc",
>   	[ilog2(I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC)] = "sfc",
> @@ -170,6 +179,7 @@ void intel_engines_add_sysfs(struct drm_i915_private *i915)
>   		&name_attr.attr,
>   		&class_attr.attr,
>   		&inst_attr.attr,
> +		&mmio_attr.attr,
>   		&caps_attr.attr,
>   		&all_caps_attr.attr,
>   		NULL
Chris Wilson Nov. 21, 2019, 1:23 p.m. UTC | #2
Quoting Lionel Landwerlin (2019-11-21 13:18:47)
> On 12/11/2019 11:28, Chris Wilson wrote:
> > Use the per-engine sysfs directory to let userspace discover the
> > mmio_base of each engine. Prior to recent generations, the user
> > accessible registers on each engine are at a fixed offset relative to
> > each engine -- but require absolute addressing. As the absolute address
> > depends on the actual physical engine, this is not always possible to
> > determine from userspace (for example icl may expose vcs1 or vcs2 as the
> > second vcs engine). Make this easy for userspace to discover by
> > providing the mmio_base in sysfs.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> 
> 
> Sounds like a good idea :
> 
> 
> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> 
> 
> I guess this being under unstable make this unsuitable to expose through 
> i915_query?

I couldn't gather enough support for a HW info i915_query :(
-Chris

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
index df263af3a9ea..abddd8d0f9ae 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_sysfs.c
@@ -48,6 +48,15 @@  inst_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
 static struct kobj_attribute inst_attr =
 __ATTR(instance, 0444, inst_show, NULL);
 
+static ssize_t
+mmio_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
+{
+	return sprintf(buf, "0x%x\n", kobj_to_engine(kobj)->mmio_base);
+}
+
+static struct kobj_attribute mmio_attr =
+__ATTR(mmio_base, 0444, mmio_show, NULL);
+
 static const char * const vcs_caps[] = {
 	[ilog2(I915_VIDEO_CLASS_CAPABILITY_HEVC)] = "hevc",
 	[ilog2(I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC)] = "sfc",
@@ -170,6 +179,7 @@  void intel_engines_add_sysfs(struct drm_i915_private *i915)
 		&name_attr.attr,
 		&class_attr.attr,
 		&inst_attr.attr,
+		&mmio_attr.attr,
 		&caps_attr.attr,
 		&all_caps_attr.attr,
 		NULL