[2/3] clk: imx8qxp: Add ADMA clocks
diff mbox series

Message ID 1573647909-31081-2-git-send-email-abel.vesa@nxp.com
State New
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Series
  • [1/3] dt-bindings: imx8-clock: Add ADMA clock ids
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Commit Message

Abel Vesa Nov. 13, 2019, 12:25 p.m. UTC
According to the RM, the Audio and DMA (ADMA) subsystem is a collection
of audio peripherals and some system modules.
Register all the ADMA specific clocks through the LPCG and CCM driver.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 drivers/clk/imx/clk-imx8qxp-lpcg.c | 42 ++++++++++++++++++++++++++++++++++++++
 drivers/clk/imx/clk-imx8qxp.c      |  8 ++++++++
 2 files changed, 50 insertions(+)

Patch
diff mbox series

diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c
index c0aff7c..78a9064 100644
--- a/drivers/clk/imx/clk-imx8qxp-lpcg.c
+++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c
@@ -77,6 +77,48 @@  static const struct imx8qxp_lpcg_data imx8qxp_lpcg_adma[] = {
 	{ IMX_ADMA_LPCG_DSP_IPG_CLK, "dsp_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 20, 0, },
 	{ IMX_ADMA_LPCG_DSP_ADB_CLK, "dsp_lpcg_adb_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 16, 0, },
 	{ IMX_ADMA_LPCG_OCRAM_IPG_CLK, "ocram_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_OCRAM_LPCG, 16, 0, },
+
+	{ IMX_ADMA_LPCG_AUD_PLL_DIV_CLK0_CLK, "aud_pll_div_clk0_lpcg_clk", "audio_pll_div_clk0_clk", 0, ADMA_PLL_CLK0_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_AUD_PLL_DIV_CLK1_CLK, "aud_pll_div_clk1_lpcg_clk", "audio_pll_div_clk1_clk", 0, ADMA_PLL_CLK1_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_AUD_REC_CLK0_CLK, "aud_rec_clk0_lpcg_clk", "audio_rec_clk0_clk", 0, ADMA_REC_CLK0_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_AUD_REC_CLK1_CLK, "aud_rec_clk1_lpcg_clk", "audio_rec_clk1_clk", 0, ADMA_REC_CLK1_LPCG, 0, 0, },
+
+	{ IMX_ADMA_LPCG_AMIX_IPG_CLK, "amix_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_AMIX_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_ESAI_0_IPG_CLK, "esai0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_ESAI_0_LPCG, 16, 0, },
+	{ IMX_ADMA_LPCG_ESAI_0_EXTAL_CLK, "esai0_lpcg_extal_clk", "acm_esai0_mclk_sel", 0, ADMA_ESAI_0_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_SAI_0_IPG_CLK, "sai0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_SAI_0_LPCG, 16, 0, },
+	{ IMX_ADMA_LPCG_SAI_0_MCLK, "sai0_lpcg_mclk", "acm_sai0_mclk_sel", 0, ADMA_SAI_0_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_SAI_1_IPG_CLK, "sai1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_SAI_1_LPCG, 16, 0, },
+	{ IMX_ADMA_LPCG_SAI_1_MCLK, "sai1_lpcg_mclk", "acm_sai1_mclk_sel", 0, ADMA_SAI_1_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_SAI_2_IPG_CLK, "sai2_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_SAI_2_LPCG, 16, 0, },
+	{ IMX_ADMA_LPCG_SAI_3_MCLK, "sai2_lpcg_mclk", "acm_sai2_mclk_sel", 0, ADMA_SAI_2_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_SAI_3_IPG_CLK, "sai3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_SAI_3_LPCG, 16, 0, },
+	{ IMX_ADMA_LPCG_SAI_3_MCLK, "sai3_lpcg_mclk", "acm_sai3_mclk_sel", 0, ADMA_SAI_3_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_SAI_4_IPG_CLK, "sai4_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_SAI_4_LPCG, 16, 0, },
+	{ IMX_ADMA_LPCG_SAI_4_MCLK, "sai4_lpcg_mclk", "acm_sai4_mclk_sel", 0, ADMA_SAI_4_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_SAI_5_IPG_CLK, "sai5_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_SAI_5_LPCG, 16, 0, },
+	{ IMX_ADMA_LPCG_SAI_5_MCLK, "sai5_lpcg_mclk", "acm_sai5_mclk_sel", 0, ADMA_SAI_5_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_MQS_IPG_CLK, "mqs_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_MQS_LPCG, 16, 0, },
+	{ IMX_ADMA_LPCG_MQS_MCLK, "mqs_lpcg_mclk", "acm_mqs_mclk_sel", 0, ADMA_MQS_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_GPT5_IPG_CLK, "gpt5_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_GPT_5_LPCG, 16, 0, },
+	{ IMX_ADMA_LPCG_GPT5_CLKIN, "gpt5_lpcg_clkin", "dma_ipg_clk_root", 0, ADMA_GPT_5_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_GPT6_IPG_CLK, "gpt6_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_GPT_6_LPCG, 16, 0, },
+	{ IMX_ADMA_LPCG_GPT6_CLKIN, "gpt6_lpcg_clkin", "dma_ipg_clk_root", 0, ADMA_GPT_6_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_GPT7_IPG_CLK, "gpt7_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_GPT_7_LPCG, 16, 0, },
+	{ IMX_ADMA_LPCG_GPT7_CLKIN, "gpt7_lpcg_clkin", "dma_ipg_clk_root", 0, ADMA_GPT_7_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_GPT8_IPG_CLK, "gpt8_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_GPT_8_LPCG, 16, 0, },
+	{ IMX_ADMA_LPCG_GPT8_CLKIN, "gpt8_lpcg_clkin", "dma_ipg_clk_root", 0, ADMA_GPT_8_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_GPT9_IPG_CLK, "gpt9_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_GPT_9_LPCG, 16, 0, },
+	{ IMX_ADMA_LPCG_GPT9_CLKIN, "gpt9_lpcg_clkin", "dma_ipg_clk_root", 0, ADMA_GPT_9_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_GPT10_IPG_CLK, "gpt10_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_GPT_10_LPCG, 16, 0, },
+	{ IMX_ADMA_LPCG_GPT10_CLKIN, "gpt10_lpcg_clkin", "dma_ipg_clk_root", 0, ADMA_GPT_10_LPCG, 0, 0, },
+
+	{ IMX_ADMA_LPCG_MCLKOUT0, "mclkout0_lpcg", "acm_mclkout0_sel", 0, ADMA_MCLKOUT0_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_MCLKOUT1, "mclkout1_lpcg", "acm_mclkout1_sel", 0, ADMA_MCLKOUT1_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_SPDIF_0_GCLKW, "spdif0_lpcg_gclkw", "dma_ipg_clk_root", 0, ADMA_SPDIF_0_LPCG, 16, 0, },
+	{ IMX_ADMA_LPCG_SPDIF_0_TX_CLK, "spdif0_lpcg_tx_clk", "acm_spdif0_mclk_sel", 0, ADMA_SPDIF_0_LPCG, 0, 0, },
+	{ IMX_ADMA_LPCG_ASRC_0_IPG_CLK, "asrc0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_ASRC_0_LPCG, 16, 0, },
+	{ IMX_ADMA_LPCG_ASRC_1_IPG_CLK, "asrc1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_ASRC_1_LPCG, 16, 0, },
 };
 
 static const struct imx8qxp_ss_lpcg imx8qxp_ss_adma = {
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index 5e2903e..5e92577 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -94,6 +94,14 @@  static int imx8qxp_clk_probe(struct platform_device *pdev)
 	clks[IMX_ADMA_PWM_CLK]		= imx_clk_scu("pwm_clk",   IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER);
 	clks[IMX_ADMA_LCD_CLK]		= imx_clk_scu("lcd_clk",   IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER);
 
+	clks[IMX_ADMA_AUD_PLL0]		= imx_clk_scu("audio_pll0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_PLL);
+	clks[IMX_ADMA_AUD_PLL1]		= imx_clk_scu("audio_pll1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_PLL);
+
+	clks[IMX_ADMA_AUD_PLL_DIV_CLK0_CLK]	= imx_clk_scu("audio_pll_div_clk0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC0);
+	clks[IMX_ADMA_AUD_PLL_DIV_CLK1_CLK]	= imx_clk_scu("audio_pll_div_clk1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC0);
+	clks[IMX_ADMA_AUD_REC_CLK0_CLK]	= imx_clk_scu("audio_rec_clk0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC1);
+	clks[IMX_ADMA_AUD_REC_CLK1_CLK]	= imx_clk_scu("audio_rec_clk1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC1);
+
 	/* Connectivity */
 	clks[IMX_CONN_SDHC0_CLK]	= imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER);
 	clks[IMX_CONN_SDHC1_CLK]	= imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER);