From patchwork Wed Nov 13 18:28:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 11242637 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CE48B930 for ; Wed, 13 Nov 2019 18:28:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A2A74206ED for ; Wed, 13 Nov 2019 18:28:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A2A74206ED Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=chris-wilson.co.uk Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A5D3A6EDE1; Wed, 13 Nov 2019 18:28:32 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [109.228.58.192]) by gabe.freedesktop.org (Postfix) with ESMTPS id 81C976EDE1; Wed, 13 Nov 2019 18:28:25 +0000 (UTC) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 19191411-1500050 for multiple; Wed, 13 Nov 2019 18:28:10 +0000 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Wed, 13 Nov 2019 18:28:08 +0000 Message-Id: <20191113182808.10780-3-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191113182808.10780-1-chris@chris-wilson.co.uk> References: <20191113182808.10780-1-chris@chris-wilson.co.uk> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 3/3] igt: Use COND_BBEND for busy spinning on gen9 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org, Joonas Lahtinen , Mika Kuoppala Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Jon Bloomfield gen9+ introduces a cmdparser for the BLT engine which copies the incoming BB to a kmd owned buffer for submission (to prevent changes being made after the bb has been safely scanned). This breaks the spin functionality because it relies on changing the submitted spin buffers in order to terminate them. Instead, for gen9+, we change the semantics by introducing a COND_BB_END into the infinite loop, to wait until a memory flag (in anothe bo) is cleared. v2: Correct nop length to avoid overwriting bb_end instr when using a dependency bo (cork) v3: fix conflicts on igt_dummyload (Mika) v4: s/bool running/uint32_t running, fix r->delta (Mika) v5: remove overzealous assert (Mika) v6: rebase on top of lib changes (Mika) v7: rework on top of public igt lib changes (Mika) v8: rebase v9: simplify by using bb end as conditional (Chris) Signed-off-by: Jon Bloomfield (v2) Cc: Joonas Lahtinen Cc: Rodrigo Vivi Cc: Mika Kuoppala Signed-off-by: Mika Kuoppala Reviewed-by: Chris Wilson --- lib/i830_reg.h | 2 +- lib/igt_dummyload.c | 17 ++++++++++++++++- lib/intel_reg.h | 3 +++ tests/i915/gem_double_irq_loop.c | 2 -- tests/i915/gem_write_read_ring_switch.c | 2 +- 5 files changed, 21 insertions(+), 5 deletions(-) diff --git a/lib/i830_reg.h b/lib/i830_reg.h index a57691c7e..410202567 100644 --- a/lib/i830_reg.h +++ b/lib/i830_reg.h @@ -43,7 +43,7 @@ /* broadwater flush bits */ #define BRW_MI_GLOBAL_SNAPSHOT_RESET (1 << 3) -#define MI_COND_BATCH_BUFFER_END (0x36<<23 | 1) +#define MI_COND_BATCH_BUFFER_END (0x36 << 23) #define MI_DO_COMPARE (1<<21) #define MI_BATCH_BUFFER_END (0xA << 23) diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c index c079bd045..652d469a0 100644 --- a/lib/igt_dummyload.c +++ b/lib/igt_dummyload.c @@ -208,7 +208,22 @@ emit_recursive_batch(igt_spin_t *spin, * trouble. See https://bugs.freedesktop.org/show_bug.cgi?id=102262 */ if (!(opts->flags & IGT_SPIN_FAST)) - cs += 1000; + cs += 960; + + if (gen >= 8) { + r = &relocs[batch->relocation_count++]; + + r->presumed_offset = 0; + r->target_handle = batch->handle; + r->offset = (cs + 2 - batch_start) * sizeof(*cs); + r->read_domains = I915_GEM_DOMAIN_COMMAND; + r->delta = (spin->condition - batch_start) * sizeof(*cs); + + *cs++ = MI_COND_BATCH_BUFFER_END | 1 << 21 | 5 << 12 | 2; + *cs++ = MI_BATCH_BUFFER_END; + *cs++ = r->delta; + *cs++ = 0; + } /* recurse */ r = &relocs[batch->relocation_count++]; diff --git a/lib/intel_reg.h b/lib/intel_reg.h index 069440cb7..10ca760a2 100644 --- a/lib/intel_reg.h +++ b/lib/intel_reg.h @@ -2593,6 +2593,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define MI_BATCH_BUFFER ((0x30 << 23) | 1) #define MI_BATCH_BUFFER_START (0x31 << 23) #define MI_BATCH_BUFFER_END (0xA << 23) +#define MI_COND_BATCH_BUFFER_END (0x36 << 23) +#define MI_DO_COMPARE (1<<21) + #define MI_BATCH_NON_SECURE (1) #define MI_BATCH_NON_SECURE_I965 (1 << 8) #define MI_BATCH_NON_SECURE_HSW (1<<13) /* Additional bit for RCS */ diff --git a/tests/i915/gem_double_irq_loop.c b/tests/i915/gem_double_irq_loop.c index b326fc58a..f17f61c19 100644 --- a/tests/i915/gem_double_irq_loop.c +++ b/tests/i915/gem_double_irq_loop.c @@ -52,8 +52,6 @@ static drm_intel_bo *target_buffer, *blt_bo; IGT_TEST_DESCRIPTION("Basic check for missed IRQs on blt ring."); -#define MI_COND_BATCH_BUFFER_END (0x36<<23 | 1) -#define MI_DO_COMPARE (1<<21) static void dummy_reloc_loop(void) { diff --git a/tests/i915/gem_write_read_ring_switch.c b/tests/i915/gem_write_read_ring_switch.c index ef229cc59..095c13c34 100644 --- a/tests/i915/gem_write_read_ring_switch.c +++ b/tests/i915/gem_write_read_ring_switch.c @@ -115,7 +115,7 @@ static void run_test(int ring) * otherwise the obj->last_write_seqno will be updated. */ if (ring == I915_EXEC_RENDER) { BEGIN_BATCH(4, 1); - OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE); + OUT_BATCH(MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | 1); OUT_BATCH(0xffffffff); /* compare dword */ OUT_RELOC(target_bo, I915_GEM_DOMAIN_RENDER, 0, 0); OUT_BATCH(MI_NOOP);