| Message ID | 20191114055155.20446-2-pgaj@cadence.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Add data hold delay support | expand |
From: Przemyslaw Gaj <pgaj@cadence.com> Date: Thu, Nov 14, 2019 at 05:51:53 > This patch adds support for THD_DEL (Data Hold Delay) to Cadence > I3C master constoller driver. > > Signed-off-by: Przemyslaw Gaj <pgaj@cadence.com> > --- > drivers/i3c/master/i3c-master-cdns.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/i3c/master/i3c-master-cdns.c b/drivers/i3c/master/i3c-master-cdns.c > index 10db0bf0655a..90ea98eef905 100644 > --- a/drivers/i3c/master/i3c-master-cdns.c > +++ b/drivers/i3c/master/i3c-master-cdns.c > @@ -60,6 +60,7 @@ > #define CTRL_HALT_EN BIT(30) > #define CTRL_MCS BIT(29) > #define CTRL_MCS_EN BIT(28) > +#define CTRL_THD_DEL(x) (((x) << 24) & GENMASK(25, 24)) > #define CTRL_HJ_DISEC BIT(8) > #define CTRL_MST_ACK BIT(7) > #define CTRL_HJ_ACK BIT(6) > @@ -1186,7 +1187,7 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m) > struct cdns_i3c_master *master = to_cdns_i3c_master(m); > unsigned long pres_step, sysclk_rate, max_i2cfreq; > struct i3c_bus *bus = i3c_master_get_bus(m); > - u32 ctrl, prescl0, prescl1, pres, low; > + u32 ctrl, prescl0, prescl1, pres, low, thd_del; > struct i3c_device_info info = { }; > int ret, ncycles; > > @@ -1264,6 +1265,8 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m) > * We will issue ENTDAA afterwards from the threaded IRQ handler. > */ > ctrl |= CTRL_HJ_ACK | CTRL_HJ_DISEC | CTRL_HALT_EN | CTRL_MCS_EN; > + if (!of_property_read_u32(m->dev.of_node, "thd_del", &thd_del)) > + ctrl |= CTRL_THD_DEL(thd_del); > writel(ctrl, master->regs + CTRL); > > cdns_i3c_master_enable(master); > -- > 2.14.0 Please change the commit message so it reflects Cadence driver. Best regards, Vitor Soares
diff --git a/drivers/i3c/master/i3c-master-cdns.c b/drivers/i3c/master/i3c-master-cdns.c index 10db0bf0655a..90ea98eef905 100644 --- a/drivers/i3c/master/i3c-master-cdns.c +++ b/drivers/i3c/master/i3c-master-cdns.c @@ -60,6 +60,7 @@ #define CTRL_HALT_EN BIT(30) #define CTRL_MCS BIT(29) #define CTRL_MCS_EN BIT(28) +#define CTRL_THD_DEL(x) (((x) << 24) & GENMASK(25, 24)) #define CTRL_HJ_DISEC BIT(8) #define CTRL_MST_ACK BIT(7) #define CTRL_HJ_ACK BIT(6) @@ -1186,7 +1187,7 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m) struct cdns_i3c_master *master = to_cdns_i3c_master(m); unsigned long pres_step, sysclk_rate, max_i2cfreq; struct i3c_bus *bus = i3c_master_get_bus(m); - u32 ctrl, prescl0, prescl1, pres, low; + u32 ctrl, prescl0, prescl1, pres, low, thd_del; struct i3c_device_info info = { }; int ret, ncycles; @@ -1264,6 +1265,8 @@ static int cdns_i3c_master_bus_init(struct i3c_master_controller *m) * We will issue ENTDAA afterwards from the threaded IRQ handler. */ ctrl |= CTRL_HJ_ACK | CTRL_HJ_DISEC | CTRL_HALT_EN | CTRL_MCS_EN; + if (!of_property_read_u32(m->dev.of_node, "thd_del", &thd_del)) + ctrl |= CTRL_THD_DEL(thd_del); writel(ctrl, master->regs + CTRL); cdns_i3c_master_enable(master);
This patch adds support for THD_DEL (Data Hold Delay) to Cadence I3C master constoller driver. Signed-off-by: Przemyslaw Gaj <pgaj@cadence.com> --- drivers/i3c/master/i3c-master-cdns.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)