| Message ID | 1573795421-13989-2-git-send-email-sanm@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3,1/1] arm64: dts: qcom: sc7180: Add USB related nodes | expand |
Hi Sandeep, On Fri, Nov 15, 2019 at 10:53:41AM +0530, Sandeep Maheswaram wrote: > Add nodes for DWC3 USB controller, QMP and QUSB PHYs. > > Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > --- > arch/arm64/boot/dts/qcom/sc7180-idp.dts | 25 ++++++++ > arch/arm64/boot/dts/qcom/sc7180.dtsi | 105 ++++++++++++++++++++++++++++++++ > 2 files changed, 130 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index 666e9b9..2c7dbdc 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > > ... > > + usb_1: usb@a6f8800 { > + compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; > + reg = <0 0x0a6f8800 0 0x400>; > + status = "disabled"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + dma-ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; > + clock-names = "cfg_noc", "core", "iface", "mock_utmi", > + "sleep"; > + > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <150000000>; > + > + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hs_phy_irq", "ss_phy_irq", > + "dm_hs_phy_irq", "dp_hs_phy_irq"; > + > + power-domains = <&gcc USB30_PRIM_GDSC>; > + > + resets = <&gcc GCC_USB30_PRIM_BCR>; > + > + usb_1_dwc3: dwc3@a600000 { > + compatible = "snps,dwc3"; > + reg = <0 0x0a600000 0 0xe000>; > + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > + iommus = <&apps_smmu 0x540 0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; > + phy-names = "usb2-phy", "usb3-phy"; > + }; I see the following message at boot: [ 4.248436] dwc3 a600000.dwc3: Failed to get clk 'ref': -2 Apparently the driver is operational regardless, however the binding lists the clocks as required: Required properties: ... - clock-names: should contain "ref", "bus_early", "suspend" - clocks: list of phandle and clock specifier pairs corresponding to entries in the clock-names property. [Documentation/devicetree/bindings/usb/dwc3.txt] The driver code also has a comment stating that the clocks should be specified: /* * Clocks are optional, but new DT platforms should support all * clocks as required by the DT-binding. */ [drivers/usb/dwc3/core.txt]
Hi Matthias, Thanks for the review. On 11/22/2019 6:21 AM, Matthias Kaehlcke wrote: > Hi Sandeep, > > On Fri, Nov 15, 2019 at 10:53:41AM +0530, Sandeep Maheswaram wrote: >> Add nodes for DWC3 USB controller, QMP and QUSB PHYs. >> >> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> >> Reviewed-by: Stephen Boyd <swboyd@chromium.org> >> --- >> arch/arm64/boot/dts/qcom/sc7180-idp.dts | 25 ++++++++ >> arch/arm64/boot/dts/qcom/sc7180.dtsi | 105 ++++++++++++++++++++++++++++++++ >> 2 files changed, 130 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi >> index 666e9b9..2c7dbdc 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi >> >> ... >> >> + usb_1: usb@a6f8800 { >> + compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; >> + reg = <0 0x0a6f8800 0 0x400>; >> + status = "disabled"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + dma-ranges; >> + >> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, >> + <&gcc GCC_USB30_PRIM_MASTER_CLK>, >> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, >> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, >> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; >> + clock-names = "cfg_noc", "core", "iface", "mock_utmi", >> + "sleep"; >> + >> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, >> + <&gcc GCC_USB30_PRIM_MASTER_CLK>; >> + assigned-clock-rates = <19200000>, <150000000>; >> + >> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "hs_phy_irq", "ss_phy_irq", >> + "dm_hs_phy_irq", "dp_hs_phy_irq"; >> + >> + power-domains = <&gcc USB30_PRIM_GDSC>; >> + >> + resets = <&gcc GCC_USB30_PRIM_BCR>; >> + >> + usb_1_dwc3: dwc3@a600000 { >> + compatible = "snps,dwc3"; >> + reg = <0 0x0a600000 0 0xe000>; >> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; >> + iommus = <&apps_smmu 0x540 0>; >> + snps,dis_u2_susphy_quirk; >> + snps,dis_enblslpm_quirk; >> + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; >> + phy-names = "usb2-phy", "usb3-phy"; >> + }; > I see the following message at boot: > > [ 4.248436] dwc3 a600000.dwc3: Failed to get clk 'ref': -2 > > Apparently the driver is operational regardless, however the binding lists > the clocks as required: > > Required properties: > ... > - clock-names: should contain "ref", "bus_early", "suspend" > - clocks: list of phandle and clock specifier pairs corresponding to > entries in the clock-names property. > > [Documentation/devicetree/bindings/usb/dwc3.txt] > > The driver code also has a comment stating that the clocks should be > specified: > > /* > * Clocks are optional, but new DT platforms should support all > * clocks as required by the DT-binding. > */ > > [drivers/usb/dwc3/core.txt] We are implenting all the required clocks in glue driver drivers/usb/dwc3/dwc3-qcom.c. Also there is exception for qcom,dwc3 in documentation Documentation/devicetree/bindings/usb/dwc3.txt Exception for clocks: clocks are optional if the parent node (i.e. glue-layer) is compatible to one of the following: "amlogic,meson-axg-dwc3" "amlogic,meson-gxl-dwc3" "cavium,octeon-7130-usb-uctl" "qcom,dwc3" "samsung,exynos5250-dwusb3" "samsung,exynos5433-dwusb3" "samsung,exynos7-dwusb3" "sprd,sc9860-dwc3" "st,stih407-dwc3" "ti,am437x-dwc3" "ti,dwc3" "ti,keystone-dwc3" "rockchip,rk3399-dwc3" "xlnx,zynqmp-dwc3"
On Wed, Nov 27, 2019 at 09:01:07AM +0000, Sandeep Maheswaram (Temp) wrote: > Hi Matthias, > > Thanks for the review. > > On 11/22/2019 6:21 AM, Matthias Kaehlcke wrote: > > Hi Sandeep, > > > > On Fri, Nov 15, 2019 at 10:53:41AM +0530, Sandeep Maheswaram wrote: > > > Add nodes for DWC3 USB controller, QMP and QUSB PHYs. > > > > > > Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> > > > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > > > --- > > > arch/arm64/boot/dts/qcom/sc7180-idp.dts | 25 ++++++++ > > > arch/arm64/boot/dts/qcom/sc7180.dtsi | 105 ++++++++++++++++++++++++++++++++ > > > 2 files changed, 130 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > > > index 666e9b9..2c7dbdc 100644 > > > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > > > > > > ... > > > > > > + usb_1: usb@a6f8800 { > > > + compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; > > > + reg = <0 0x0a6f8800 0 0x400>; > > > + status = "disabled"; > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + ranges; > > > + dma-ranges; > > > + > > > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > > > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > > > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > > > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > > > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; > > > + clock-names = "cfg_noc", "core", "iface", "mock_utmi", > > > + "sleep"; > > > + > > > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > > > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > > > + assigned-clock-rates = <19200000>, <150000000>; > > > + > > > + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; > > > + interrupt-names = "hs_phy_irq", "ss_phy_irq", > > > + "dm_hs_phy_irq", "dp_hs_phy_irq"; > > > + > > > + power-domains = <&gcc USB30_PRIM_GDSC>; > > > + > > > + resets = <&gcc GCC_USB30_PRIM_BCR>; > > > + > > > + usb_1_dwc3: dwc3@a600000 { > > > + compatible = "snps,dwc3"; > > > + reg = <0 0x0a600000 0 0xe000>; > > > + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > > > + iommus = <&apps_smmu 0x540 0>; > > > + snps,dis_u2_susphy_quirk; > > > + snps,dis_enblslpm_quirk; > > > + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; > > > + phy-names = "usb2-phy", "usb3-phy"; > > > + }; > > I see the following message at boot: > > > > [ 4.248436] dwc3 a600000.dwc3: Failed to get clk 'ref': -2 > > > > Apparently the driver is operational regardless, however the binding lists > > the clocks as required: > > > > Required properties: > > ... > > - clock-names: should contain "ref", "bus_early", "suspend" > > - clocks: list of phandle and clock specifier pairs corresponding to > > entries in the clock-names property. > > > > [Documentation/devicetree/bindings/usb/dwc3.txt] > > > > The driver code also has a comment stating that the clocks should be > > specified: > > > > /* > > * Clocks are optional, but new DT platforms should support all > > * clocks as required by the DT-binding. > > */ > > > > [drivers/usb/dwc3/core.txt] > We are implenting all the required clocks in glue driver > drivers/usb/dwc3/dwc3-qcom.c. > > Also there is exception for qcom,dwc3 in documentation > > Documentation/devicetree/bindings/usb/dwc3.txt > > > Exception for clocks: > > clocks are optional if the parent node (i.e. glue-layer) is compatible to > one of the following: > "amlogic,meson-axg-dwc3" > "amlogic,meson-gxl-dwc3" > "cavium,octeon-7130-usb-uctl" > "qcom,dwc3" > "samsung,exynos5250-dwusb3" > "samsung,exynos5433-dwusb3" > "samsung,exynos7-dwusb3" > "sprd,sc9860-dwc3" > "st,stih407-dwc3" > "ti,am437x-dwc3" > "ti,dwc3" > "ti,keystone-dwc3" > "rockchip,rk3399-dwc3" > "xlnx,zynqmp-dwc3" ah, I missed this, thanks for the pointer!
On Thu 21 Nov 16:51 PST 2019, Matthias Kaehlcke wrote: > Hi Sandeep, > > On Fri, Nov 15, 2019 at 10:53:41AM +0530, Sandeep Maheswaram wrote: > > Add nodes for DWC3 USB controller, QMP and QUSB PHYs. > > > > Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> > > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > > --- > > arch/arm64/boot/dts/qcom/sc7180-idp.dts | 25 ++++++++ > > arch/arm64/boot/dts/qcom/sc7180.dtsi | 105 ++++++++++++++++++++++++++++++++ > > 2 files changed, 130 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > > index 666e9b9..2c7dbdc 100644 > > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > > > > ... > > > > + usb_1: usb@a6f8800 { > > + compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; > > + reg = <0 0x0a6f8800 0 0x400>; > > + status = "disabled"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + dma-ranges; > > + > > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; > > + clock-names = "cfg_noc", "core", "iface", "mock_utmi", > > + "sleep"; > > + > > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > > + assigned-clock-rates = <19200000>, <150000000>; > > + > > + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "hs_phy_irq", "ss_phy_irq", > > + "dm_hs_phy_irq", "dp_hs_phy_irq"; > > + > > + power-domains = <&gcc USB30_PRIM_GDSC>; > > + > > + resets = <&gcc GCC_USB30_PRIM_BCR>; > > + > > + usb_1_dwc3: dwc3@a600000 { > > + compatible = "snps,dwc3"; > > + reg = <0 0x0a600000 0 0xe000>; > > + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > > + iommus = <&apps_smmu 0x540 0>; > > + snps,dis_u2_susphy_quirk; > > + snps,dis_enblslpm_quirk; > > + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; > > + phy-names = "usb2-phy", "usb3-phy"; > > + }; > > I see the following message at boot: > > [ 4.248436] dwc3 a600000.dwc3: Failed to get clk 'ref': -2 > dwc3-qcom picks up the clocks per the names of the binding, but then dwc3 tries to pick up the same clocks based on the generic names. At some point it would be nice to figure out how to have these two play nice with each other, but for now it's a "harmless" error print - which has consumed many hours of unnecessary debugging by various people... Regards, Bjorn
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index 189254f..282d33e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -400,3 +400,28 @@ bias-pull-up; }; }; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + status = "okay"; + vdd-supply = <&vreg_l4a_0p8>; + vdda-pll-supply = <&vreg_l11a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l17a_3p0>; + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; + qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; + qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; +}; + +&usb_1_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l4a_0p8>; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 666e9b9..2c7dbdc 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/qcom,gcc-sc7180.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy-qcom-qusb2.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / { @@ -182,6 +183,18 @@ #power-domain-cells = <1>; }; + qfprom@784000 { + compatible = "qcom,qfprom"; + reg = <0 0x00784000 0 0x8ff>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2p_hstx_trim: hstx-trim-primary@25b { + reg = <0x25b 0x1>; + bits = <1 3>; + }; + }; + qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x6000>; @@ -911,6 +924,98 @@ status = "disabled"; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sc7180-qusb2-phy"; + reg = <0 0x088e3000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb", "ref"; + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + nvmem-cells = <&qusb2p_hstx_trim>; + }; + + usb_1_qmpphy: phy@88e9000 { + compatible = "qcom,sc7180-qmp-usb3-phy"; + reg = <0 0x088e9000 0 0x18c>, + <0 0x088e8000 0 0x38>; + reg-names = "reg-base", "dp_com"; + status = "disabled"; + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "com_aux"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + usb_1_ssphy: lanes@88e9200 { + reg = <0 0x088e9200 0 0x128>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x218>, + <0 0x088e9600 0 0x128>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x18>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <150000000>; + + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + usb_1_dwc3: dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xe000>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x540 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>,