diff mbox series

[v2,1/8] clk: qcom: alpha-pll: Remove useless read from set rate

Message ID 1573812304-24074-2-git-send-email-tdas@codeaurora.org (mailing list archive)
State Accepted, archived
Headers show
Series Add GPU & Video Clock controller driver for SC7180 | expand

Commit Message

Taniya Das Nov. 15, 2019, 10:04 a.m. UTC
PLL_MODE read in fabia set rate is not required, thus remove the same.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.

Comments

Stephen Boyd Dec. 24, 2019, 6:37 a.m. UTC | #1
Quoting Taniya Das (2019-11-15 02:04:57)
> PLL_MODE read in fabia set rate is not required, thus remove the same.
> 
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---

Applied to clk-next
diff mbox series

Patch

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 055318f..e39034d 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -1141,14 +1141,9 @@  static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
 						unsigned long prate)
 {
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
-	u32 val, l, alpha_width = pll_alpha_width(pll);
+	u32 l, alpha_width = pll_alpha_width(pll);
 	u64 a;
 	unsigned long rrate;
-	int ret = 0;
-
-	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
-	if (ret)
-		return ret;

 	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);