arm64: dts: rockchip: Enable PCIe for Radxa Rock Pi 4 board
diff mbox series

Message ID 20191115180825.10526-1-matwey@sai.msu.ru
State New
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Series
  • arm64: dts: rockchip: Enable PCIe for Radxa Rock Pi 4 board
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Commit Message

Matwey V. Kornilov Nov. 15, 2019, 6:08 p.m. UTC
Radxa Rock Pi 4 is equipped with M.2 PCIe slot,
so enable PCIe for the board.

The changes has been tested with Intel SSD 660p series device.

    01:00.0 Class 0108: Device 8086:f1a8 (rev 03)

Signed-off-by: Matwey V. Kornilov <matwey@sai.msu.ru>
---
 arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

Comments

Heiko Stuebner Nov. 15, 2019, 6:14 p.m. UTC | #1
Hi Matwey,

Am Freitag, 15. November 2019, 19:08:21 CET schrieb Matwey V. Kornilov:
> Radxa Rock Pi 4 is equipped with M.2 PCIe slot,
> so enable PCIe for the board.
> 
> The changes has been tested with Intel SSD 660p series device.
> 
>     01:00.0 Class 0108: Device 8086:f1a8 (rev 03)
> 
> Signed-off-by: Matwey V. Kornilov <matwey@sai.msu.ru>
> ---
>  arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
> index 1ae1ebd4efdd..9c2927faba41 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
> @@ -463,6 +463,20 @@
>  	pmu1830-supply = <&vcc_3v0>;
>  };
>  
> +&pcie_phy {
> +	status = "okay";
> +};
> +
> +&pcie0 {
> +	status = "okay";
> +
> +	ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
> +	num-lanes = <4>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie_clkreqnb_cpm>;
> +	max-link-speed = <2>;

the RockPi schematics should be available, so could you also check
the supply regulators and add them please?

Thanks
Heiko


> +};
> +
>  &pinctrl {
>  	bt {
>  		bt_enable_h: bt-enable-h {
>
Matwey V. Kornilov Nov. 15, 2019, 6:16 p.m. UTC | #2
пт, 15 нояб. 2019 г. в 21:14, Heiko Stübner <heiko@sntech.de>:
>
> Hi Matwey,
>
> Am Freitag, 15. November 2019, 19:08:21 CET schrieb Matwey V. Kornilov:
> > Radxa Rock Pi 4 is equipped with M.2 PCIe slot,
> > so enable PCIe for the board.
> >
> > The changes has been tested with Intel SSD 660p series device.
> >
> >     01:00.0 Class 0108: Device 8086:f1a8 (rev 03)
> >
> > Signed-off-by: Matwey V. Kornilov <matwey@sai.msu.ru>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
> > index 1ae1ebd4efdd..9c2927faba41 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
> > @@ -463,6 +463,20 @@
> >       pmu1830-supply = <&vcc_3v0>;
> >  };
> >
> > +&pcie_phy {
> > +     status = "okay";
> > +};
> > +
> > +&pcie0 {
> > +     status = "okay";
> > +
> > +     ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
> > +     num-lanes = <4>;
> > +     pinctrl-names = "default";
> > +     pinctrl-0 = <&pcie_clkreqnb_cpm>;
> > +     max-link-speed = <2>;
>
> the RockPi schematics should be available, so could you also check
> the supply regulators and add them please?
>
> Thanks
> Heiko

Hi,

What do you mean? pcie 3.3v regulator is already in dts. I've checked
that its gpio is correctly configured.

>
>
> > +};
> > +
> >  &pinctrl {
> >       bt {
> >               bt_enable_h: bt-enable-h {
> >
>
>
>
>

Patch
diff mbox series

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
index 1ae1ebd4efdd..9c2927faba41 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
@@ -463,6 +463,20 @@ 
 	pmu1830-supply = <&vcc_3v0>;
 };
 
+&pcie_phy {
+	status = "okay";
+};
+
+&pcie0 {
+	status = "okay";
+
+	ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
+	num-lanes = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_clkreqnb_cpm>;
+	max-link-speed = <2>;
+};
+
 &pinctrl {
 	bt {
 		bt_enable_h: bt-enable-h {