From patchwork Mon Nov 18 10:07:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 11249261 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1CE05109A for ; Mon, 18 Nov 2019 10:08:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id F1D322075E for ; Mon, 18 Nov 2019 10:08:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="Bqq+Z9Ni" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726874AbfKRKIU (ORCPT ); Mon, 18 Nov 2019 05:08:20 -0500 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:47017 "EHLO us-smtp-delivery-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726460AbfKRKIT (ORCPT ); Mon, 18 Nov 2019 05:08:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1574071699; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SuEdHgpSfnqJ4t9uIksCSEzHcYIlpI9neglm8kr4jHA=; b=Bqq+Z9NiLPsLPNwrknytIeHfENP/6VZkJsIxI+7WV5B3lEmM4HHPmyrfOpOiXuqu2eXLLB cym7vWrg2yPLH+gtDGi2IlDNpbYqhEu/ceYXHTXKYJRg7h2iiFR5b1mSfW1eeXu5cMB/gx QNgmURhDRKEUddSJxIeDsF0t50j2uto= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-295-Xz-aM7d-NBObScfusYInwA-1; Mon, 18 Nov 2019 05:08:17 -0500 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 5D61C1802CEA; Mon, 18 Nov 2019 10:08:16 +0000 (UTC) Received: from t460s.redhat.com (unknown [10.36.118.85]) by smtp.corp.redhat.com (Postfix) with ESMTP id A168B66856; Mon, 18 Nov 2019 10:08:14 +0000 (UTC) From: David Hildenbrand To: kvm@vger.kernel.org Cc: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= , Thomas Huth , Christian Borntraeger , Cornelia Huck , Janosch Frank , David Hildenbrand Subject: [kvm-unit-tests PULL 06/12] s390x: Add CR save area Date: Mon, 18 Nov 2019 11:07:13 +0100 Message-Id: <20191118100719.7968-7-david@redhat.com> In-Reply-To: <20191118100719.7968-1-david@redhat.com> References: <20191118100719.7968-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-MC-Unique: Xz-aM7d-NBObScfusYInwA-1 X-Mimecast-Spam-Score: 0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Janosch Frank If we run with DAT enabled and do a reset, we need to save the CRs to backup our ASCEs on a diag308 for example. Reviewed-by: Thomas Huth Signed-off-by: Janosch Frank Message-Id: <20191111153345.22505-3-frankja@linux.ibm.com> Signed-off-by: David Hildenbrand --- lib/s390x/asm-offsets.c | 2 +- lib/s390x/asm/arch_def.h | 4 ++-- lib/s390x/interrupt.c | 4 ++-- lib/s390x/smp.c | 2 +- s390x/cstart64.S | 10 +++++----- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/lib/s390x/asm-offsets.c b/lib/s390x/asm-offsets.c index 6e2d259..4b213f8 100644 --- a/lib/s390x/asm-offsets.c +++ b/lib/s390x/asm-offsets.c @@ -57,7 +57,7 @@ int main(void) OFFSET(GEN_LC_SW_INT_GRS, lowcore, sw_int_grs); OFFSET(GEN_LC_SW_INT_FPRS, lowcore, sw_int_fprs); OFFSET(GEN_LC_SW_INT_FPC, lowcore, sw_int_fpc); - OFFSET(GEN_LC_SW_INT_CR0, lowcore, sw_int_cr0); + OFFSET(GEN_LC_SW_INT_CRS, lowcore, sw_int_crs); OFFSET(GEN_LC_MCCK_EXT_SA_ADDR, lowcore, mcck_ext_sa_addr); OFFSET(GEN_LC_FPRS_SA, lowcore, fprs_sa); OFFSET(GEN_LC_GRS_SA, lowcore, grs_sa); diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h index 96cca2e..07d4e5e 100644 --- a/lib/s390x/asm/arch_def.h +++ b/lib/s390x/asm/arch_def.h @@ -78,8 +78,8 @@ struct lowcore { uint64_t sw_int_fprs[16]; /* 0x0280 */ uint32_t sw_int_fpc; /* 0x0300 */ uint8_t pad_0x0304[0x0308 - 0x0304]; /* 0x0304 */ - uint64_t sw_int_cr0; /* 0x0308 */ - uint8_t pad_0x0310[0x11b0 - 0x0310]; /* 0x0310 */ + uint64_t sw_int_crs[16]; /* 0x0308 */ + uint8_t pad_0x0310[0x11b0 - 0x0388]; /* 0x0388 */ uint64_t mcck_ext_sa_addr; /* 0x11b0 */ uint8_t pad_0x11b8[0x1200 - 0x11b8]; /* 0x11b8 */ uint64_t fprs_sa[16]; /* 0x1200 */ diff --git a/lib/s390x/interrupt.c b/lib/s390x/interrupt.c index 1636207..3e07867 100644 --- a/lib/s390x/interrupt.c +++ b/lib/s390x/interrupt.c @@ -124,13 +124,13 @@ void handle_ext_int(void) } if (lc->ext_int_code == EXT_IRQ_SERVICE_SIG) { - lc->sw_int_cr0 &= ~(1UL << 9); + lc->sw_int_crs[0] &= ~(1UL << 9); sclp_handle_ext(); } else { ext_int_expected = false; } - if (!(lc->sw_int_cr0 & CR0_EXTM_MASK)) + if (!(lc->sw_int_crs[0] & CR0_EXTM_MASK)) lc->ext_old_psw.mask &= ~PSW_MASK_EXT; } diff --git a/lib/s390x/smp.c b/lib/s390x/smp.c index 7602886..f57f420 100644 --- a/lib/s390x/smp.c +++ b/lib/s390x/smp.c @@ -189,7 +189,7 @@ int smp_cpu_setup(uint16_t addr, struct psw psw) cpu->lowcore->sw_int_grs[15] = (uint64_t)cpu->stack + (PAGE_SIZE * 4); lc->restart_new_psw.mask = 0x0000000180000000UL; lc->restart_new_psw.addr = (uint64_t)smp_cpu_setup_state; - lc->sw_int_cr0 = 0x0000000000040000UL; + lc->sw_int_crs[0] = 0x0000000000040000UL; /* Start processing */ rc = sigp_retry(cpu->addr, SIGP_RESTART, 0, NULL); diff --git a/s390x/cstart64.S b/s390x/cstart64.S index 043e34a..4be20fc 100644 --- a/s390x/cstart64.S +++ b/s390x/cstart64.S @@ -92,8 +92,8 @@ memsetxc: .macro SAVE_REGS /* save grs 0-15 */ stmg %r0, %r15, GEN_LC_SW_INT_GRS - /* save cr0 */ - stctg %c0, %c0, GEN_LC_SW_INT_CR0 + /* save crs 0-15 */ + stctg %c0, %c15, GEN_LC_SW_INT_CRS /* load a cr0 that has the AFP control bit which enables all FPRs */ larl %r1, initial_cr0 lctlg %c0, %c0, 0(%r1) @@ -112,8 +112,8 @@ memsetxc: ld \i, \i * 8(%r1) .endr lfpc GEN_LC_SW_INT_FPC - /* restore cr0 */ - lctlg %c0, %c0, GEN_LC_SW_INT_CR0 + /* restore crs 0-15 */ + lctlg %c0, %c15, GEN_LC_SW_INT_CRS /* restore grs 0-15 */ lmg %r0, %r15, GEN_LC_SW_INT_GRS .endm @@ -150,7 +150,7 @@ diag308_load_reset: smp_cpu_setup_state: xgr %r1, %r1 lmg %r0, %r15, GEN_LC_SW_INT_GRS - lctlg %c0, %c0, GEN_LC_SW_INT_CR0 + lctlg %c0, %c0, GEN_LC_SW_INT_CRS br %r14 pgm_int: