[v3,3/4] RISC-V: Introduce a new config for SBI v0.1

Commit Message

Atish Patra Nov. 18, 2019, 10:45 p.m. UTC

We now have SBI v0.2 which is more scalable and extendable to handle
future needs for RISC-V supervisor interfaces.

Introduce a new config and move all SBI v0.1 code under that config.
This allows to implement the new replacement SBI extensions cleanly
and remove v0.1 extensions easily in future. Currently, the config
is enabled by default. Once all M-mode software with v0.1 are no
longer in use, this config option and all relevant code can be easily
removed.

Signed-off-by: Atish Patra <[e-mail]>
---
 arch/riscv/Kconfig      |  6 ++++
 arch/riscv/kernel/sbi.c | 69 +++++++++++++++++++++++++++++------------
 2 files changed, 55 insertions(+), 20 deletions(-)

Patch

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8eebbc8860bb..4881b87d0d14 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -272,6 +272,12 @@  menu "Kernel features"
 
 source "kernel/Kconfig.hz"
 
+config RISCV_SBI_V01
+	bool "SBI v0.1 support"
+	default y
+	help
+	  This config allows kernel to use SBI v0.1 APIs. This will be
+	  deprecated in future once legacy M-mode software are no longer in use.
 endmenu
 
 menu "Boot options"
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 1cee3ef009bb..6c864fd7fb95 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -52,6 +52,7 @@  int sbi_err_map_linux_errno(int err)
 	};
 }
 
+#ifdef CONFIG_RISCV_SBI_V01
 /**
  * sbi_console_putchar() - Writes given character to the console device.
  * @ch: The data to be written to the console.
@@ -78,39 +79,47 @@  int sbi_console_getchar(void)
 }
 
 /**
- * sbi_set_timer() - Program the timer for next timer event.
- * @stime_value: The value after which next timer event should fire.
+ * sbi_shutdown() - Remove all the harts from executing supervisor code.
  *
  * Return: None
  */
-void sbi_set_timer(uint64_t stime_value)
+void sbi_shutdown(void)
 {
-#if __riscv_xlen == 32
-	sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
-			  stime_value >> 32, 0, 0, 0, 0);
-#else
-	sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
-#endif
+	sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
 }
 
 /**
- * sbi_shutdown() - Remove all the harts from executing supervisor code.
+ * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
  *
  * Return: None
  */
-void sbi_shutdown(void)
+void sbi_clear_ipi(void)
 {
-	sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
+	sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
 }
 
+#endif
+
 /**
- * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
+ * sbi_set_timer() - Program the timer for next timer event.
+ * @stime_value: The value after which next timer event should fire.
  *
  * Return: None
  */
-void sbi_clear_ipi(void)
+void sbi_set_timer(uint64_t stime_value)
 {
-	sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
+#ifdef CONFIG_RISCV_SBI_V01
+	if (sbi_spec_is_0_1()) {
+#if __riscv_xlen == 32
+		sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
+			  stime_value >> 32, 0, 0, 0, 0);
+#else
+		sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
+#endif
+		return;
+	}
+#endif
+
 }
 
 /**
@@ -121,8 +130,13 @@  void sbi_clear_ipi(void)
  */
 void sbi_send_ipi(const unsigned long *hart_mask)
 {
-	sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
+#ifdef CONFIG_RISCV_SBI_V01
+	if (sbi_spec_is_0_1()) {
+		sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
 			0, 0, 0, 0, 0);
+		return;
+	}
+#endif
 }
 
 /**
@@ -133,8 +147,13 @@  void sbi_send_ipi(const unsigned long *hart_mask)
  */
 void sbi_remote_fence_i(const unsigned long *hart_mask)
 {
-	sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask,
-			0, 0, 0, 0, 0);
+#ifdef CONFIG_RISCV_SBI_V01
+	if (sbi_spec_is_0_1()) {
+		sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0,
+			 (unsigned long)hart_mask, 0, 0, 0, 0, 0);
+		return;
+	}
+#endif
 }
 
 /**
@@ -150,8 +169,13 @@  void sbi_remote_sfence_vma(const unsigned long *hart_mask,
 					 unsigned long start,
 					 unsigned long size)
 {
-	sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
+#ifdef CONFIG_RISCV_SBI_V01
+	if (sbi_spec_is_0_1()) {
+		sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
 			(unsigned long)hart_mask, start, size, 0, 0, 0);
+		return;
+	}
+#endif
 }
 
 /**
@@ -170,8 +194,13 @@  void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
 					      unsigned long size,
 					      unsigned long asid)
 {
-	sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
+#ifdef CONFIG_RISCV_SBI_V01
+	if (sbi_spec_is_0_1()) {
+		sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
 			(unsigned long)hart_mask, start, size, asid, 0, 0);
+		return;
+	}
+#endif
 }
 
 /**