From patchwork Tue Nov 19 02:19:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 11250647 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2DEE114C0 for ; Tue, 19 Nov 2019 02:20:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0C82A22316 for ; Tue, 19 Nov 2019 02:20:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="sLG2UfeN" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0C82A22316 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LXHzGGAWAS+q4kl2fNCQJPN5y5Ipahn2UVjyII2SjQw=; b=sLG2UfeNFreTwF uMq0uMENmjuc7VYZdqlrfI2/ym4oD3pmRF26frbYCo5vK7L0fclbZDu38CtVsVDA2clth1RLywtEm p0E5HJty8CEMUd9v4murjJtr5TkSPme2u3uT29gYBsiMO1K7wt+XW/A15YV/xly24oTKG68RBTUjq zSaGmskSTMCpmpSFMkbzV8WvNng7O60tMl5YTWoXKF1wnTOZQRt7v28bSL7D+naRJlXqUh31SrgiN keXgwQBAkNAWumY+3HfL71K78qgCzZrqaqdzZ021hVVqLbL6iy720co1IBTAvUq5RnHutgR9vEhbi ULxihL7/MjKc15c8HZ3A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iWt7y-0008NT-Ob; Tue, 19 Nov 2019 02:20:26 +0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iWt70-0006SA-CN; Tue, 19 Nov 2019 02:19:34 +0000 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id C52C2B32F; Tue, 19 Nov 2019 02:19:23 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Subject: [PATCH v4 4/8] irqchip: rtd1195-mux: Add RTD1195 definitions Date: Tue, 19 Nov 2019 03:19:13 +0100 Message-Id: <20191119021917.15917-5-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191119021917.15917-1-afaerber@suse.de> References: <20191119021917.15917-1-afaerber@suse.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191118_181926_734015_F5722ACE X-CRM114-Status: GOOD ( 10.67 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [195.135.220.15 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Cooper , Marc Zyngier , linux-kernel@vger.kernel.org, Thomas Gleixner , =?utf-8?q?Andreas_F=C3=A4rber?= , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add compatible strings and bit mappings for Realtek RTD1195 SoC. Signed-off-by: Andreas Färber --- v3 -> v4: * Use tabular formatting (Thomas) * Adopt different braces style (Thomas) * Updated with shortened isr_to_int_en_mask callback name (Thomas) * Renamed functions and variables from rtd119x_ to rtd1195_ * Renamed enum values from RTD119X_ to RTD1195_ v3: New drivers/irqchip/irq-rtd1195-mux.c | 101 +++++++++++++++++++++++++++++++++++++- 1 file changed, 100 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c index e6b08438b23c..765d72653383 100644 --- a/drivers/irqchip/irq-rtd1195-mux.c +++ b/drivers/irqchip/irq-rtd1195-mux.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Realtek RTD1295 IRQ mux + * Realtek RTD1195/RTD1295 IRQ mux * * Copyright (c) 2017-2019 Andreas Färber */ @@ -132,6 +132,81 @@ static const struct irq_domain_ops rtd1195_mux_irq_domain_ops = { .map = rtd1195_mux_irq_domain_map, }; +enum rtd1195_iso_isr_bits { + RTD1195_ISO_ISR_TC3_SHIFT = 1, + RTD1195_ISO_ISR_UR0_SHIFT = 2, + RTD1195_ISO_ISR_IRDA_SHIFT = 5, + RTD1195_ISO_ISR_WDOG_NMI_SHIFT = 7, + RTD1195_ISO_ISR_I2C0_SHIFT = 8, + RTD1195_ISO_ISR_TC4_SHIFT = 9, + RTD1195_ISO_ISR_I2C6_SHIFT = 10, + RTD1195_ISO_ISR_RTC_HSEC_SHIFT = 12, + RTD1195_ISO_ISR_RTC_ALARM_SHIFT = 13, + RTD1195_ISO_ISR_VFD_WDONE_SHIFT = 14, + RTD1195_ISO_ISR_VFD_ARDKPADA_SHIFT = 15, + RTD1195_ISO_ISR_VFD_ARDKPADDA_SHIFT = 16, + RTD1195_ISO_ISR_VFD_ARDSWA_SHIFT = 17, + RTD1195_ISO_ISR_VFD_ARDSWDA_SHIFT = 18, + RTD1195_ISO_ISR_GPIOA_SHIFT = 19, + RTD1195_ISO_ISR_GPIODA_SHIFT = 20, + RTD1195_ISO_ISR_CEC_SHIFT = 22, +}; + +static const u32 rtd1195_iso_isr_to_scpu_int_en_mask[32] = { + [RTD1195_ISO_ISR_UR0_SHIFT] = BIT(2), + [RTD1195_ISO_ISR_IRDA_SHIFT] = BIT(5), + [RTD1195_ISO_ISR_I2C0_SHIFT] = BIT(8), + [RTD1195_ISO_ISR_I2C6_SHIFT] = BIT(10), + [RTD1195_ISO_ISR_RTC_HSEC_SHIFT] = BIT(12), + [RTD1195_ISO_ISR_RTC_ALARM_SHIFT] = BIT(13), + [RTD1195_ISO_ISR_VFD_WDONE_SHIFT] = BIT(14), + [RTD1195_ISO_ISR_VFD_ARDKPADA_SHIFT] = BIT(15), + [RTD1195_ISO_ISR_VFD_ARDKPADDA_SHIFT] = BIT(16), + [RTD1195_ISO_ISR_VFD_ARDSWA_SHIFT] = BIT(17), + [RTD1195_ISO_ISR_VFD_ARDSWDA_SHIFT] = BIT(18), + [RTD1195_ISO_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1195_ISO_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1195_ISO_ISR_CEC_SHIFT] = BIT(22), +}; + +enum rtd1195_misc_isr_bits { + RTD1195_MIS_ISR_WDOG_NMI_SHIFT = 2, + RTD1195_MIS_ISR_UR1_SHIFT = 3, + RTD1195_MIS_ISR_I2C1_SHIFT = 4, + RTD1195_MIS_ISR_UR1_TO_SHIFT = 5, + RTD1195_MIS_ISR_TC0_SHIFT = 6, + RTD1195_MIS_ISR_TC1_SHIFT = 7, + RTD1195_MIS_ISR_RTC_HSEC_SHIFT = 9, + RTD1195_MIS_ISR_RTC_MIN_SHIFT = 10, + RTD1195_MIS_ISR_RTC_HOUR_SHIFT = 11, + RTD1195_MIS_ISR_RTC_DATE_SHIFT = 12, + RTD1195_MIS_ISR_I2C5_SHIFT = 14, + RTD1195_MIS_ISR_I2C4_SHIFT = 15, + RTD1195_MIS_ISR_GPIOA_SHIFT = 19, + RTD1195_MIS_ISR_GPIODA_SHIFT = 20, + RTD1195_MIS_ISR_LSADC_SHIFT = 21, + RTD1195_MIS_ISR_I2C3_SHIFT = 23, + RTD1195_MIS_ISR_I2C2_SHIFT = 26, + RTD1195_MIS_ISR_GSPI_SHIFT = 27, +}; + +static const u32 rtd1195_misc_isr_to_scpu_int_en_mask[32] = { + [RTD1195_MIS_ISR_UR1_SHIFT] = BIT(3), + [RTD1195_MIS_ISR_I2C1_SHIFT] = BIT(4), + [RTD1195_MIS_ISR_UR1_TO_SHIFT] = BIT(5), + [RTD1195_MIS_ISR_RTC_MIN_SHIFT] = BIT(10), + [RTD1195_MIS_ISR_RTC_HOUR_SHIFT] = BIT(11), + [RTD1195_MIS_ISR_RTC_DATE_SHIFT] = BIT(12), + [RTD1195_MIS_ISR_I2C5_SHIFT] = BIT(14), + [RTD1195_MIS_ISR_I2C4_SHIFT] = BIT(15), + [RTD1195_MIS_ISR_GPIOA_SHIFT] = BIT(19), + [RTD1195_MIS_ISR_GPIODA_SHIFT] = BIT(20), + [RTD1195_MIS_ISR_LSADC_SHIFT] = BIT(21), + [RTD1195_MIS_ISR_I2C2_SHIFT] = BIT(26), + [RTD1195_MIS_ISR_GSPI_SHIFT] = BIT(27), + [RTD1195_MIS_ISR_I2C3_SHIFT] = BIT(28), +}; + enum rtd1295_iso_isr_bits { RTD1295_ISO_ISR_UR0_SHIFT = 2, RTD1295_ISO_ISR_IRDA_SHIFT = 5, @@ -202,6 +277,13 @@ static const u32 rtd1295_misc_isr_to_scpu_int_en_mask[32] = { [RTD1295_ISR_FAN_SHIFT] = BIT(29), }; +static const struct rtd1195_irq_mux_info rtd1195_iso_irq_mux_info = { + .isr_offset = 0x0, + .umsk_isr_offset = 0x4, + .scpu_int_en_offset = 0x40, + .isr_to_int_en_mask = rtd1195_iso_isr_to_scpu_int_en_mask, +}; + static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = { .isr_offset = 0x0, .umsk_isr_offset = 0x4, @@ -209,6 +291,13 @@ static const struct rtd1195_irq_mux_info rtd1295_iso_irq_mux_info = { .isr_to_int_en_mask = rtd1295_iso_isr_to_scpu_int_en_mask, }; +static const struct rtd1195_irq_mux_info rtd1195_misc_irq_mux_info = { + .umsk_isr_offset = 0x8, + .isr_offset = 0xc, + .scpu_int_en_offset = 0x80, + .isr_to_int_en_mask = rtd1195_misc_isr_to_scpu_int_en_mask, +}; + static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = { .umsk_isr_offset = 0x8, .isr_offset = 0xc, @@ -217,10 +306,18 @@ static const struct rtd1195_irq_mux_info rtd1295_misc_irq_mux_info = { }; static const struct of_device_id rtd1295_irq_mux_dt_matches[] = { + { + .compatible = "realtek,rtd1195-iso-irq-mux", + .data = &rtd1195_iso_irq_mux_info, + }, { .compatible = "realtek,rtd1295-iso-irq-mux", .data = &rtd1295_iso_irq_mux_info, }, + { + .compatible = "realtek,rtd1195-misc-irq-mux", + .data = &rtd1195_misc_irq_mux_info, + }, { .compatible = "realtek,rtd1295-misc-irq-mux", .data = &rtd1295_misc_irq_mux_info, @@ -279,5 +376,7 @@ static int __init rtd1195_irq_mux_init(struct device_node *node, return 0; } +IRQCHIP_DECLARE(rtd1195_iso_mux, "realtek,rtd1195-iso-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1295_iso_mux, "realtek,rtd1295-iso-irq-mux", rtd1195_irq_mux_init); +IRQCHIP_DECLARE(rtd1195_misc_mux, "realtek,rtd1195-misc-irq-mux", rtd1195_irq_mux_init); IRQCHIP_DECLARE(rtd1295_misc_mux, "realtek,rtd1295-misc-irq-mux", rtd1195_irq_mux_init);