From patchwork Tue Nov 19 06:50:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11250941 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9F623138C for ; Tue, 19 Nov 2019 06:52:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7D7C122318 for ; Tue, 19 Nov 2019 06:52:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="Lh51bIPT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727506AbfKSGvz (ORCPT ); Tue, 19 Nov 2019 01:51:55 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:14279 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727801AbfKSGvK (ORCPT ); Tue, 19 Nov 2019 01:51:10 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 18 Nov 2019 22:51:07 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 18 Nov 2019 22:51:10 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 18 Nov 2019 22:51:10 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 19 Nov 2019 06:51:09 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 19 Nov 2019 06:51:09 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.175.254]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 18 Nov 2019 22:51:09 -0800 From: Sowjanya Komatineni To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH v1 12/17] arm: tegra: Add clock-cells property to Tegra pmc Date: Mon, 18 Nov 2019 22:50:29 -0800 Message-ID: <1574146234-3871-13-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> References: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1574146267; bh=UxINdMwtmQ5rxM0ZUPV5wKmTIo6gbx7kHXvFFoRj8Qw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Lh51bIPT3acwHX6DBDS7OfjjiVAVyVL+e3gTXqGKlZUN5+aHyTRC1EhyNmDhnZ4jQ 2JK1vHIbEtpB2TFONjbQ5Nz1Hzefsh/BYFk98KTJ5QATSel+Da9rYf4aLCo0iz06dP vDZSVX5R8O7eGhMOu/G7HFt2WciXwTau8hbGDMfEDVEv363YA+DehiogQ+BKZnyMzw K/DUyR/X91/uWefC4BEg8HzLAbApEWB9FtN1JaYcBcTix5obl635VGlkvP+n0FXOFc p07AA/rSDIHhFZWkCShts/xKje0h3AJPFjN6Soaf/QEqyBU3xqW+2tobxBD0F/Wql2 OVQ2Zx8MpwbXA== Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Tegra pmc has 3 clocks clk_out_1, clk_out_2, clk_out_3 with mux and gate for each of these clocks as part of pmc and Tegra pmc is the clock provider for these clocks. This patch adds #clock-cells property with 1 clock specifier to the Tegra pmc node. Signed-off-by: Sowjanya Komatineni --- arch/arm/boot/dts/tegra114.dtsi | 4 +++- arch/arm/boot/dts/tegra124.dtsi | 4 +++- arch/arm/boot/dts/tegra30.dtsi | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 0d7a6327e404..b8f12f24f314 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra114"; @@ -514,11 +515,12 @@ status = "disabled"; }; - pmc@7000e400 { + pmc: pmc@7000e400 { compatible = "nvidia,tegra114-pmc"; reg = <0x7000e400 0x400>; clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; }; fuse@7000f800 { diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 413bfb981de8..d0802c4ae3bf 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra124"; @@ -595,11 +596,12 @@ clocks = <&tegra_car TEGRA124_CLK_RTC>; }; - pmc@7000e400 { + pmc: pmc@7000e400 { compatible = "nvidia,tegra124-pmc"; reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; }; fuse@7000f800 { diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 55ae050042ce..4d5e9d0001d3 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra30"; @@ -714,11 +715,12 @@ status = "disabled"; }; - pmc@7000e400 { + pmc: pmc@7000e400 { compatible = "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>; clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; }; mc: memory-controller@7000f000 {