| Message ID | 20191119133145.31466-1-peter.maydell@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, 19 Nov 2019 at 13:31, Peter Maydell <peter.maydell@linaro.org> wrote: > > Target-arm queue for rc2 -- just some minor bugfixes. > > thanks > -- PMM > > The following changes since commit 6e5d4999c761ffa082f60d72a14e5c953515b417: > > Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-11-19' into staging (2019-11-19 11:29:01 +0000) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191119 > > for you to fetch changes up to 04c9c81b8fa2ee33f59a26265700fae6fc646062: > > target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY (2019-11-19 13:20:28 +0000) > > ---------------------------------------------------------------- > target-arm queue: > * Support EL0 v7m msr/mrs for CONFIG_USER_ONLY > * Relax r13 restriction for ldrex/strex for v8.0 > * Do not reject rt == rt2 for strexd > * net/cadence_gem: Set PHY autonegotiation restart status > * ssi: xilinx_spips: Skip spi bus update for a few register writes > * pl031: Expose RTCICR as proper WC register > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/4.2 for any user-visible changes. -- PMM
Target-arm queue for rc2 -- just some minor bugfixes. thanks -- PMM The following changes since commit 6e5d4999c761ffa082f60d72a14e5c953515b417: Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-11-19' into staging (2019-11-19 11:29:01 +0000) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191119 for you to fetch changes up to 04c9c81b8fa2ee33f59a26265700fae6fc646062: target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY (2019-11-19 13:20:28 +0000) ---------------------------------------------------------------- target-arm queue: * Support EL0 v7m msr/mrs for CONFIG_USER_ONLY * Relax r13 restriction for ldrex/strex for v8.0 * Do not reject rt == rt2 for strexd * net/cadence_gem: Set PHY autonegotiation restart status * ssi: xilinx_spips: Skip spi bus update for a few register writes * pl031: Expose RTCICR as proper WC register ---------------------------------------------------------------- Alexander Graf (1): pl031: Expose RTCICR as proper WC register Linus Ziegert (1): net/cadence_gem: Set PHY autonegotiation restart status Richard Henderson (4): target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller target/arm: Do not reject rt == rt2 for strexd target/arm: Relax r13 restriction for ldrex/strex for v8.0 target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY Sai Pavan Boddu (1): ssi: xilinx_spips: Skip spi bus update for a few register writes target/arm/cpu.h | 5 +-- hw/net/cadence_gem.c | 9 ++-- hw/rtc/pl031.c | 6 +-- hw/ssi/xilinx_spips.c | 22 ++++++++-- target/arm/cpu64.c | 15 ------- target/arm/helper.c | 9 +++- target/arm/m_helper.c | 114 ++++++++++++++++++++++++++++++------------------- target/arm/translate.c | 14 +++--- 8 files changed, 113 insertions(+), 81 deletions(-)