| Message ID | 1574172496-12987-6-git-send-email-abel.vesa@nxp.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | clk: imx: Trivial cleanups for clk_hw based API | expand |
On 2019-11-19 4:08 PM, Abel Vesa wrote: > Renaming the imx_clk_frac_pll and imx_clk_sccg_pll register functions to > imx_clk_hw_frac_pll, respectively imx_clk_hw_sccg_pll to be more obvious > that they are clk_hw based On a somewake unrelated note there is no "SCCG", reference manual refers to this as "SSCG": "Spread Sprectum Clock Generator" These wrapping macros don't correctly forward null or error either. > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > --- > drivers/clk/imx/clk-frac-pll.c | 7 ++++--- > drivers/clk/imx/clk-sccg-pll.c | 4 ++-- > drivers/clk/imx/clk.h | 12 ++++++++++-- > 3 files changed, 16 insertions(+), 7 deletions(-) > > diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c > index fece503..101e0a3 100644 > --- a/drivers/clk/imx/clk-frac-pll.c > +++ b/drivers/clk/imx/clk-frac-pll.c > @@ -201,8 +201,9 @@ static const struct clk_ops clk_frac_pll_ops = { > .set_rate = clk_pll_set_rate, > }; > > -struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, > - void __iomem *base) > +struct clk_hw *imx_clk_hw_frac_pll(const char *name, > + const char *parent_name, > + void __iomem *base) > { > struct clk_init_data init; > struct clk_frac_pll *pll; > @@ -230,5 +231,5 @@ struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, > return ERR_PTR(ret); > } > > - return hw->clk; > + return hw; > } > diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c > index 5d65f65..2cf8748 100644 > --- a/drivers/clk/imx/clk-sccg-pll.c > +++ b/drivers/clk/imx/clk-sccg-pll.c > @@ -506,7 +506,7 @@ static const struct clk_ops clk_sccg_pll_ops = { > .determine_rate = clk_sccg_pll_determine_rate, > }; > > -struct clk *imx_clk_sccg_pll(const char *name, > +struct clk_hw *imx_clk_hw_sccg_pll(const char *name, > const char * const *parent_names, > u8 num_parents, > u8 parent, u8 bypass1, u8 bypass2, > @@ -545,5 +545,5 @@ struct clk *imx_clk_sccg_pll(const char *name, > return ERR_PTR(ret); > } > > - return hw->clk; > + return hw; > } > diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h > index 71b21ab..15c6f54 100644 > --- a/drivers/clk/imx/clk.h > +++ b/drivers/clk/imx/clk.h > @@ -115,6 +115,14 @@ extern struct imx_pll14xx_clk imx_1443x_pll; > #define imx_clk_pllv2(name, parent, base) \ > imx_clk_hw_pllv2(name, parent, base)->clk > > +#define imx_clk_frac_pll(name, parent_name, base) \ > + imx_clk_hw_frac_pll(name, parent_name, base)->clk > + > +#define imx_clk_sccg_pll(name, parent_names, num_parents, parent,\ > + bypass1, bypass2, base, flags) \ > + imx_clk_hw_sccg_pll(name, parent_names, num_parents, parent,\ > + bypass1, bypass2, base, flags)->clk \ > + > struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, > void __iomem *base, const struct imx_pll14xx_clk *pll_clk); > > @@ -124,10 +132,10 @@ struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name, > struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent, > void __iomem *base); > > -struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, > +struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name, > void __iomem *base); > > -struct clk *imx_clk_sccg_pll(const char *name, > +struct clk_hw *imx_clk_hw_sccg_pll(const char *name, > const char * const *parent_names, > u8 num_parents, > u8 parent, u8 bypass1, u8 bypass2, >
diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c index fece503..101e0a3 100644 --- a/drivers/clk/imx/clk-frac-pll.c +++ b/drivers/clk/imx/clk-frac-pll.c @@ -201,8 +201,9 @@ static const struct clk_ops clk_frac_pll_ops = { .set_rate = clk_pll_set_rate, }; -struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, - void __iomem *base) +struct clk_hw *imx_clk_hw_frac_pll(const char *name, + const char *parent_name, + void __iomem *base) { struct clk_init_data init; struct clk_frac_pll *pll; @@ -230,5 +231,5 @@ struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, return ERR_PTR(ret); } - return hw->clk; + return hw; } diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c index 5d65f65..2cf8748 100644 --- a/drivers/clk/imx/clk-sccg-pll.c +++ b/drivers/clk/imx/clk-sccg-pll.c @@ -506,7 +506,7 @@ static const struct clk_ops clk_sccg_pll_ops = { .determine_rate = clk_sccg_pll_determine_rate, }; -struct clk *imx_clk_sccg_pll(const char *name, +struct clk_hw *imx_clk_hw_sccg_pll(const char *name, const char * const *parent_names, u8 num_parents, u8 parent, u8 bypass1, u8 bypass2, @@ -545,5 +545,5 @@ struct clk *imx_clk_sccg_pll(const char *name, return ERR_PTR(ret); } - return hw->clk; + return hw; } diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 71b21ab..15c6f54 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -115,6 +115,14 @@ extern struct imx_pll14xx_clk imx_1443x_pll; #define imx_clk_pllv2(name, parent, base) \ imx_clk_hw_pllv2(name, parent, base)->clk +#define imx_clk_frac_pll(name, parent_name, base) \ + imx_clk_hw_frac_pll(name, parent_name, base)->clk + +#define imx_clk_sccg_pll(name, parent_names, num_parents, parent,\ + bypass1, bypass2, base, flags) \ + imx_clk_hw_sccg_pll(name, parent_names, num_parents, parent,\ + bypass1, bypass2, base, flags)->clk \ + struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, void __iomem *base, const struct imx_pll14xx_clk *pll_clk); @@ -124,10 +132,10 @@ struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name, struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent, void __iomem *base); -struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, +struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name, void __iomem *base); -struct clk *imx_clk_sccg_pll(const char *name, +struct clk_hw *imx_clk_hw_sccg_pll(const char *name, const char * const *parent_names, u8 num_parents, u8 parent, u8 bypass1, u8 bypass2,
Renaming the imx_clk_frac_pll and imx_clk_sccg_pll register functions to imx_clk_hw_frac_pll, respectively imx_clk_hw_sccg_pll to be more obvious that they are clk_hw based. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- drivers/clk/imx/clk-frac-pll.c | 7 ++++--- drivers/clk/imx/clk-sccg-pll.c | 4 ++-- drivers/clk/imx/clk.h | 12 ++++++++++-- 3 files changed, 16 insertions(+), 7 deletions(-)