| Message ID | 20191120002254.13842-1-srinivas.pandruvada@linux.intel.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Delegated to: | Andy Shevchenko |
| Headers | show |
| Series | tools/power/x86/intel-speed-select: Display TRL buckets for just base config level | expand |
diff --git a/tools/power/x86/intel-speed-select/isst-core.c b/tools/power/x86/intel-speed-select/isst-core.c index aa19c9998e6c..d14c7bcd327a 100644 --- a/tools/power/x86/intel-speed-select/isst-core.c +++ b/tools/power/x86/intel-speed-select/isst-core.c @@ -681,6 +681,7 @@ int isst_get_process_ctdp(int cpu, int tdp_level, struct isst_pkg_ctdp *pkg_dev) } isst_get_get_trl_from_msr(cpu, ctdp_level->trl_sse_active_cores); + isst_get_trl_bucket_info(cpu, &ctdp_level->buckets_info); continue; }
When only base config level is present, this tool is displaying TRL (Turbo-ratio-limits) by reading legacy MSR. In this case, also present core count for TRL by reading MSR 0x1AE. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> --- tools/power/x86/intel-speed-select/isst-core.c | 1 + 1 file changed, 1 insertion(+)