[PATCHv9,06/12] PCI: mobiveil: Add callback function for link up check
diff mbox series

Message ID 20191120034451.30102-7-Zhiqiang.Hou@nxp.com
State Superseded
Delegated to: Lorenzo Pieralisi
Headers show
Series
  • PCI: Recode Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs
Related show

Commit Message

Zhiqiang Hou Nov. 20, 2019, 3:45 a.m. UTC
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The platforms, in which the Mobiveil GPEX is integrated,
may have their specific mechanism to check link up status.
This patch is to enable these platforms to implement theirs.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V9:
 - New patch splited from the #1 of V8 patches to make it easy to review.

 drivers/pci/controller/mobiveil/pcie-mobiveil.c | 3 +++
 drivers/pci/controller/mobiveil/pcie-mobiveil.h | 5 +++++
 2 files changed, 8 insertions(+)

Comments

Andrew Murray Jan. 13, 2020, 11:22 a.m. UTC | #1
On Wed, Nov 20, 2019 at 03:45:57AM +0000, Z.q. Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> The platforms, in which the Mobiveil GPEX is integrated,
> may have their specific mechanism to check link up status.
> This patch is to enable these platforms to implement theirs.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V9:
>  - New patch splited from the #1 of V8 patches to make it easy to review.
> 
>  drivers/pci/controller/mobiveil/pcie-mobiveil.c | 3 +++
>  drivers/pci/controller/mobiveil/pcie-mobiveil.h | 5 +++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> index 2773f823c9ea..b9ed2d95641c 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> @@ -125,6 +125,9 @@ void mobiveil_csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off,
>  
>  bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
>  {
> +	if (pcie->ops->link_up)
> +		return pcie->ops->link_up(pcie);
> +
>  	return (mobiveil_csr_readl(pcie, LTSSM_STATUS) &
>  		LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;

On the previous patch I suggested that we don't mix up the link_up logic
with the logic that decides which function to call. In this case the link_up
logic is trivial. So this is probably OK.

Reviewed-by: Andrew Murray <andrew.murray@arm.com>

>  }
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> index 18d85806a7fc..95d2e7c809b8 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> @@ -148,6 +148,10 @@ struct root_port {
>  	struct pci_host_bridge *bridge;
>  };
>  
> +struct mobiveil_pab_ops {
> +	int (*link_up)(struct mobiveil_pcie *pcie);
> +};
> +
>  struct mobiveil_pcie {
>  	struct platform_device *pdev;
>  	void __iomem *csr_axi_slave_base;	/* root port config base */
> @@ -157,6 +161,7 @@ struct mobiveil_pcie {
>  	int ppio_wins;
>  	int ob_wins_configured;		/* configured outbound windows */
>  	int ib_wins_configured;		/* configured inbound windows */
> +	const struct mobiveil_pab_ops *ops;
>  	struct root_port rp;
>  };
>  
> -- 
> 2.17.1
>
Zhiqiang Hou Feb. 6, 2020, 1:25 p.m. UTC | #2
Hi Andrew,

Thanks a lot for your review!

B.R,
Zhiqiang

> -----Original Message-----
> From: Andrew Murray <andrew.murray@arm.com>
> Sent: 2020年1月13日 19:22
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; arnd@arndb.de;
> mark.rutland@arm.com; l.subrahmanya@mobiveil.co.in;
> shawnguo@kernel.org; m.karthikeyan@mobiveil.co.in; Leo Li
> <leoyang.li@nxp.com>; lorenzo.pieralisi@arm.com;
> catalin.marinas@arm.com; will.deacon@arm.com; Mingkai Hu
> <mingkai.hu@nxp.com>; M.h. Lian <minghuan.lian@nxp.com>; Xiaowei Bao
> <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv9 06/12] PCI: mobiveil: Add callback function for link up
> check
> 
> On Wed, Nov 20, 2019 at 03:45:57AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > The platforms, in which the Mobiveil GPEX is integrated, may have
> > their specific mechanism to check link up status.
> > This patch is to enable these platforms to implement theirs.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
> > V9:
> >  - New patch splited from the #1 of V8 patches to make it easy to review.
> >
> >  drivers/pci/controller/mobiveil/pcie-mobiveil.c | 3 +++
> > drivers/pci/controller/mobiveil/pcie-mobiveil.h | 5 +++++
> >  2 files changed, 8 insertions(+)
> >
> > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> > b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> > index 2773f823c9ea..b9ed2d95641c 100644
> > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
> > @@ -125,6 +125,9 @@ void mobiveil_csr_write(struct mobiveil_pcie
> > *pcie, u32 val, u32 off,
> >
> >  bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)  {
> > +	if (pcie->ops->link_up)
> > +		return pcie->ops->link_up(pcie);
> > +
> >  	return (mobiveil_csr_readl(pcie, LTSSM_STATUS) &
> >  		LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;
> 
> On the previous patch I suggested that we don't mix up the link_up logic with
> the logic that decides which function to call. In this case the link_up logic is
> trivial. So this is probably OK.
> 
> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
> 
> >  }
> > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> > b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> > index 18d85806a7fc..95d2e7c809b8 100644
> > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> > @@ -148,6 +148,10 @@ struct root_port {
> >  	struct pci_host_bridge *bridge;
> >  };
> >
> > +struct mobiveil_pab_ops {
> > +	int (*link_up)(struct mobiveil_pcie *pcie); };
> > +
> >  struct mobiveil_pcie {
> >  	struct platform_device *pdev;
> >  	void __iomem *csr_axi_slave_base;	/* root port config base */
> > @@ -157,6 +161,7 @@ struct mobiveil_pcie {
> >  	int ppio_wins;
> >  	int ob_wins_configured;		/* configured outbound windows */
> >  	int ib_wins_configured;		/* configured inbound windows */
> > +	const struct mobiveil_pab_ops *ops;
> >  	struct root_port rp;
> >  };
> >
> > --
> > 2.17.1
> >

Patch
diff mbox series

diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
index 2773f823c9ea..b9ed2d95641c 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
@@ -125,6 +125,9 @@  void mobiveil_csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off,
 
 bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
 {
+	if (pcie->ops->link_up)
+		return pcie->ops->link_up(pcie);
+
 	return (mobiveil_csr_readl(pcie, LTSSM_STATUS) &
 		LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;
 }
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
index 18d85806a7fc..95d2e7c809b8 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
@@ -148,6 +148,10 @@  struct root_port {
 	struct pci_host_bridge *bridge;
 };
 
+struct mobiveil_pab_ops {
+	int (*link_up)(struct mobiveil_pcie *pcie);
+};
+
 struct mobiveil_pcie {
 	struct platform_device *pdev;
 	void __iomem *csr_axi_slave_base;	/* root port config base */
@@ -157,6 +161,7 @@  struct mobiveil_pcie {
 	int ppio_wins;
 	int ob_wins_configured;		/* configured outbound windows */
 	int ib_wins_configured;		/* configured inbound windows */
+	const struct mobiveil_pab_ops *ops;
 	struct root_port rp;
 };