@@ -148,13 +148,13 @@ static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
static void
wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
- u32 val)
+ u32 val, bool readable)
{
struct i915_wa wa = {
.reg = reg,
.mask = mask,
.val = val,
- .read = mask,
+ .read = readable ? mask : 0,
};
_wa_add(wal, &wa);
@@ -163,29 +163,30 @@ wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
static void
wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
- wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val));
+ wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val), true);
}
static void
wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
- wa_write_masked_or(wal, reg, ~0, val);
+ wa_write_masked_or(wal, reg, ~0, val, true);
}
static void
wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
- wa_write_masked_or(wal, reg, val, val);
+ wa_write_masked_or(wal, reg, val, val, true);
}
#define WA_SET_BIT_MASKED(addr, mask) \
- wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
+ wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask), true)
#define WA_CLR_BIT_MASKED(addr, mask) \
- wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_DISABLE(mask))
+ wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_DISABLE(mask), true)
#define WA_SET_FIELD_MASKED(addr, mask, value) \
- wa_write_masked_or(wal, (addr), (mask), _MASKED_FIELD((mask), (value)))
+ wa_write_masked_or(wal, (addr), (mask), _MASKED_FIELD((mask), \
+ (value)), true)
static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
@@ -553,7 +554,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_write_masked_or(wal,
GEN10_CACHE_MODE_SS,
0, /* write-only, so skip validation */
- _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE));
+ _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE),
+ true);
/* WaDisableGPGPUMidThreadPreemption:icl */
WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1,
@@ -827,7 +829,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
DRM_DEBUG_DRIVER("MCR slice/subslice = %x\n", mcr);
- wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
+ wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr, true);
}
static void
@@ -861,7 +863,7 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
wa_write_masked_or(wal,
GEN11_GACB_PERF_CTRL,
GEN11_HASH_CTRL_MASK,
- GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
+ GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4, true);
/* Wa_1405766107:icl
* Formerly known as WaCL2SFHalfMaxAlloc
@@ -1359,11 +1361,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_write_masked_or(wal,
GEN8_GARBCNTL,
GEN11_HASH_CTRL_EXCL_MASK,
- GEN11_HASH_CTRL_EXCL_BIT0);
+ GEN11_HASH_CTRL_EXCL_BIT0, true);
wa_write_masked_or(wal,
GEN11_GLBLINVL,
GEN11_BANK_HASH_ADDR_EXCL_MASK,
- GEN11_BANK_HASH_ADDR_EXCL_BIT0);
+ GEN11_BANK_HASH_ADDR_EXCL_BIT0, true);
/*
* Wa_1405733216:icl
@@ -1395,7 +1397,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
wa_write_masked_or(wal,
GEN11_SCRATCH2,
GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
- 0);
+ 0, true);
}
if (IS_GEN_RANGE(i915, 9, 11)) {
@@ -1436,7 +1438,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN8_L3SQCREG1,
L3_PRIO_CREDITS_MASK,
L3_GENERAL_PRIO_CREDITS(62) |
- L3_HIGH_PRIO_CREDITS(2));
+ L3_HIGH_PRIO_CREDITS(2), true);
/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
wa_write_or(wal,
WA infrastructure is extended to record the WA register readability for verification purpose. With this, if a WA register is not readable for any reasons, verification will be skipped for that WA. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 +++++++++++---------- 1 file changed, 17 insertions(+), 15 deletions(-)