[3/3] drm/i915: Skip the Wa_1604555607 verification
diff mbox series

Message ID 20191120164020.21352-4-ramalingam.c@intel.com
State New
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Series
  • Wa_1604555607 implementation and verification skip
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Commit Message

Ramalingam C Nov. 20, 2019, 4:40 p.m. UTC
At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Comments

Tvrtko Ursulin Nov. 20, 2019, 4:55 p.m. UTC | #1
On 20/11/2019 16:40, Ramalingam C wrote:
> At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> disabling the WA verification.
> 
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 8c441bf10cb1..0a3034e841c4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -580,7 +580,10 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>   	val = intel_uncore_read(engine->uncore, FF_MODE2);
>   	val &= ~FF_MODE2_TDS_TIMER_MASK;
>   	val |= FF_MODE2_TDS_TIMER_128;
> -	wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, true);
> +	/* At TGL A0 silicon FF_MODE2 reg read is not functional. */
> +	wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> +			   !IS_TGL_REVID(engine->uncore->i915, 0,
> +					 TGL_REVID_A0));

Why do you need the previous patch and can't just re-add the helper (we 
had it at some point) which creates the workaround with wa->read = 0 
directly?

wa_write_masked_or__no_verify, or __wa_write_masked_or with read mask 
explicitly passed in?

Regards,

Tvrtko

>   }
>   
>   static void
>
Ramalingam C Nov. 20, 2019, 5:33 p.m. UTC | #2
On 2019-11-20 at 16:55:35 +0000, Tvrtko Ursulin wrote:
> 
> On 20/11/2019 16:40, Ramalingam C wrote:
> > At TGL A0 stepping, FF_MODE2 register read back is broken, hence
> > disabling the WA verification.
> > 
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++++-
> >   1 file changed, 4 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 8c441bf10cb1..0a3034e841c4 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -580,7 +580,10 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >   	val = intel_uncore_read(engine->uncore, FF_MODE2);
> >   	val &= ~FF_MODE2_TDS_TIMER_MASK;
> >   	val |= FF_MODE2_TDS_TIMER_128;
> > -	wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, true);
> > +	/* At TGL A0 silicon FF_MODE2 reg read is not functional. */
> > +	wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> > +			   !IS_TGL_REVID(engine->uncore->i915, 0,
> > +					 TGL_REVID_A0));
> 
> Why do you need the previous patch and can't just re-add the helper (we had
> it at some point) which creates the workaround with wa->read = 0 directly?
> 
> wa_write_masked_or__no_verify, or __wa_write_masked_or with read mask
> explicitly passed in?
Thanks Tvrtko. That helped to avoid many changes across file.
implemented wa_write_masked_or__no_verify

-Ram
> 
> Regards,
> 
> Tvrtko
> 
> >   }
> >   static void
> >

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 8c441bf10cb1..0a3034e841c4 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -580,7 +580,10 @@  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	val = intel_uncore_read(engine->uncore, FF_MODE2);
 	val &= ~FF_MODE2_TDS_TIMER_MASK;
 	val |= FF_MODE2_TDS_TIMER_128;
-	wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val, true);
+	/* At TGL A0 silicon FF_MODE2 reg read is not functional. */
+	wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
+			   !IS_TGL_REVID(engine->uncore->i915, 0,
+					 TGL_REVID_A0));
 }
 
 static void