[2/2] drm/i915: Skip the Wa_1604555607 verification
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Message ID 20191121054406.25605-1-ramalingam.c@intel.com
State New
Headers show
Series
  • Untitled series #206309
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Commit Message

Ramalingam C Nov. 21, 2019, 5:44 a.m. UTC
At TGL A0 stepping, FF_MODE2 register read back is broken, hence
disabling the WA verification.

Helper function called wa_write_masked_or_no_verify is defined for the
same purpose.

v2:
  i915 ptr retrieved from engine. [Tvrtko]

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 93efefa205d6..05086840951b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -160,6 +160,20 @@  wa_write_masked_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
 	_wa_add(wal, &wa);
 }
 
+static void
+wa_write_masked_or_no_verify(struct i915_wa_list *wal, i915_reg_t reg, u32 mask,
+		   u32 val)
+{
+	struct i915_wa wa = {
+		.reg  = reg,
+		.mask = mask,
+		.val  = val,
+		.read = 0,
+	};
+
+	_wa_add(wal, &wa);
+}
+
 static void
 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 {
@@ -578,7 +592,11 @@  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	val = intel_uncore_read(engine->uncore, FF_MODE2);
 	val &= ~FF_MODE2_TDS_TIMER_MASK;
 	val |= FF_MODE2_TDS_TIMER_128;
-	wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
+	if (IS_TGL_REVID(engine->i915, 0, TGL_REVID_A0))
+		wa_write_masked_or_no_verify(wal, FF_MODE2,
+					     FF_MODE2_TDS_TIMER_MASK, val);
+	else
+		wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
 }
 
 static void