| Message ID | 1574611468-3319-1-git-send-email-gaurav.k.singh@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Enable PSR2 in next iteration of suspend-resume/S0ix cycling | expand |
Hi Gaurav As we already talked, on upstream for now we do not want to recovery of PSR runtime errors, so not merging this patch. But if you want comments in this patch to merge in your kernel tree...I would change the commit title to: "Do not mark as sink as not reliable to PSR runtime errors" or something similar as the changes here will not only affect during suspend-resume cycling. Also I would change it to only do not set sink_not_reliable in case of CRC mismatch leaving the other errors setting sink_not_reliable, if doing so changing the commit message suggested above. On Sun, 2019-11-24 at 21:34 +0530, Gaurav K Singh wrote: > In case of CRC mismatch, panel generates IRQ_HD and > PSR2 gets disabled by i915 driver. Due to this, PSR2 will > only be enabled back only if system is rebooted or cold boot. > So, in cases of suspend resume stress test and S0ix stress test, > when we encounter this CRC issue on a particular iteration, > once PSR2 is disabled,it remains disabled throughout all the > cycling iterations until the system is rebooted. > > Keeping this in mind, many times users do not reboot their system and > they just keep lid off/on or suspend/resume. In these scenarios > in case of CRC issue, panel will become non-PSR2 which will > eventually > drain out battery. > > In order to fix this behavior, did not set the "sink_not_reliable" > flag > to be true, so that intel_psr_compute_config() can pass in case of a > normal modeset which will lead to enabling PSR2 again in next > iteration > of suspend/resume or S0ix cycle(without reboot). > > Tested this patch and works fine on Gen9 Intel chromebook, PSR2 was > enabled back in next iteration, no other sideeffects observed. > > Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index c1d133362b76..8465d0fc2214 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1420,10 +1420,9 @@ void intel_psr_short_pulse(struct intel_dp > *intel_dp) > if (val & ~errors) > DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n", > val & ~errors); > - if (val & errors) { > + if (val & errors) > intel_psr_disable_locked(intel_dp); > - psr->sink_not_reliable = true; > - } > + > /* clear status register */ > drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val); > exit:
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index c1d133362b76..8465d0fc2214 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1420,10 +1420,9 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp) if (val & ~errors) DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n", val & ~errors); - if (val & errors) { + if (val & errors) intel_psr_disable_locked(intel_dp); - psr->sink_not_reliable = true; - } + /* clear status register */ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val); exit:
In case of CRC mismatch, panel generates IRQ_HD and PSR2 gets disabled by i915 driver. Due to this, PSR2 will only be enabled back only if system is rebooted or cold boot. So, in cases of suspend resume stress test and S0ix stress test, when we encounter this CRC issue on a particular iteration, once PSR2 is disabled,it remains disabled throughout all the cycling iterations until the system is rebooted. Keeping this in mind, many times users do not reboot their system and they just keep lid off/on or suspend/resume. In these scenarios in case of CRC issue, panel will become non-PSR2 which will eventually drain out battery. In order to fix this behavior, did not set the "sink_not_reliable" flag to be true, so that intel_psr_compute_config() can pass in case of a normal modeset which will lead to enabling PSR2 again in next iteration of suspend/resume or S0ix cycle(without reboot). Tested this patch and works fine on Gen9 Intel chromebook, PSR2 was enabled back in next iteration, no other sideeffects observed. Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)