| Message ID | 20191126231717.76703-1-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/display/tgl: Do not program clockgating | expand |
On Wed, 2019-11-27 at 11:11 +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915/display/tgl: Do not program clockgating > URL : https://patchwork.freedesktop.org/series/70076/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_7426_full -> Patchwork_15450_full > ==================================================== > > Summary > ------- > > **FAILURE** > > Serious unknown changes coming with Patchwork_15450_full absolutely > need to be > verified manually. > > If you think the reported changes have nothing to do with the > changes > introduced in Patchwork_15450_full, please notify your bug team to > allow them > to document this new failure mode, which will reduce false > positives in CI. > > > > Possible new issues > ------------------- > > Here are the unknown changes that may have been introduced in > Patchwork_15450_full: > > ### IGT changes ### > > #### Possible regressions #### > > * igt@kms_big_fb@y-tiled-8bpp-rotate-180: > - shard-skl: [PASS][1] -> [INCOMPLETE][2] +1 similar > issue > [1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-skl10/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html > [2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-skl3/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html This changes are not affecting SKL, SKL don't have native TC ports so it will always return in "if (tc_port == PORT_TC_NONE)" > > > Known issues > ------------ > > Here are the changes found in Patchwork_15450_full that come from > known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_ctx_isolation@rcs0-s3: > - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) > [3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-apl2/igt@gem_ctx_isolation@rcs0-s3.html > [4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-apl1/igt@gem_ctx_isolation@rcs0-s3.html > > * igt@gem_exec_create@forked: > - shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([fdo#108838] > / [fdo#111747]) > [5]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-tglb1/igt@gem_exec_create@forked.html > [6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-tglb3/igt@gem_exec_create@forked.html > > * igt@gem_exec_parallel@fds: > - shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([fdo#111867]) > [7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-tglb4/igt@gem_exec_parallel@fds.html > [8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-tglb6/igt@gem_exec_parallel@fds.html > > * igt@gem_mmap_gtt@hang: > - shard-snb: [PASS][9] -> [INCOMPLETE][10] > ([fdo#105411]) > [9]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-snb2/igt@gem_mmap_gtt@hang.html > [10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-snb7/igt@gem_mmap_gtt@hang.html > > * igt@gem_ppgtt@flink-and-close-vma-leak: > - shard-glk: [PASS][11] -> [FAIL][12] ([fdo#112392]) > [11]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-glk3/igt@gem_ppgtt@flink-and-close-vma-leak.html > [12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-glk2/igt@gem_ppgtt@flink-and-close-vma-leak.html > - shard-apl: [PASS][13] -> [FAIL][14] ([fdo#112392]) > [13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-apl4/igt@gem_ppgtt@flink-and-close-vma-leak.html > [14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-apl7/igt@gem_ppgtt@flink-and-close-vma-leak.html > > * igt@gem_softpin@noreloc-s3: > - shard-skl: [PASS][15] -> [INCOMPLETE][16] > ([fdo#104108]) > [15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-skl4/igt@gem_softpin@noreloc-s3.html > [16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-skl5/igt@gem_softpin@noreloc-s3.html > > * igt@gem_userptr_blits@sync-unmap-after-close: > - shard-hsw: [PASS][17] -> [DMESG-WARN][18] > ([fdo#111870]) +1 similar issue > [17]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-hsw8/igt@gem_userptr_blits@sync-unmap-after-close.html > [18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-hsw6/igt@gem_userptr_blits@sync-unmap-after-close.html > - shard-snb: [PASS][19] -> [DMESG-WARN][20] > ([fdo#110789] / [fdo#111870]) > [19]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-snb1/igt@gem_userptr_blits@sync-unmap-after-close.html > [20]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-snb1/igt@gem_userptr_blits@sync-unmap-after-close.html > > * igt@kms_big_fb@x-tiled-16bpp-rotate-180: > - shard-skl: [PASS][21] -> [INCOMPLETE][22] > ([fdo#112409]) > [21]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-skl9/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html > [22]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-skl1/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html > > * igt@kms_big_fb@x-tiled-32bpp-rotate-0: > - shard-skl: [PASS][23] -> [INCOMPLETE][24] > ([fdo#112347]) +2 similar issues > [23]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-skl1/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html > [24]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-skl4/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html > > * igt@kms_big_fb@y-tiled-16bpp-rotate-180: > - shard-glk: [PASS][25] -> [INCOMPLETE][26] > ([fdo#103359] / [k.org#198133]) > [25]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-glk8/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html > [26]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-glk8/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html > > * igt@kms_big_fb@y-tiled-32bpp-rotate-0: > - shard-skl: [PASS][27] -> [INCOMPLETE][28] > ([fdo#104108] / [fdo#112347]) > [27]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-skl9/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html > [28]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-skl2/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html > > * igt@kms_big_fb@y-tiled-8bpp-rotate-0: > - shard-kbl: [PASS][29] -> [INCOMPLETE][30] > ([fdo#103665]) +1 similar issue > [29]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-kbl4/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html > [30]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-kbl7/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html > > * igt@kms_cursor_crc@pipe-a-cursor-suspend: > - shard-kbl: [PASS][31] -> [DMESG-WARN][32] > ([fdo#108566]) +2 similar issues > [31]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html > [32]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html > > * igt@kms_cursor_legacy@pipe-a-forked-move: > - shard-hsw: [PASS][33] -> [INCOMPLETE][34] > ([fdo#103540]) > [33]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-hsw2/igt@kms_cursor_legacy@pipe-a-forked-move.html > [34]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-hsw8/igt@kms_cursor_legacy@pipe-a-forked-move.html > > * igt@kms > _frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc: > - shard-tglb: [PASS][35] -> [INCOMPLETE][36] > ([fdo#111884]) > [35]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html > [36]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc.html > > * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt: > - shard-tglb: [PASS][37] -> [FAIL][38] ([fdo#103167]) +3 > similar issues > [37]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html > [38]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html > > * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt: > - shard-iclb: [PASS][39] -> [FAIL][40] ([fdo#103167]) > [39]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html > [40]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html > > > #### Possible fixes #### > > * igt@gem_eio@in-flight-suspend: > - shard-tglb: [INCOMPLETE][41] ([fdo#111832] / > [fdo#111850] / [fdo#112081]) -> [PASS][42] > [41]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-tglb2/igt@gem_eio@in-flight-suspend.html > [42]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-tglb1/igt@gem_eio@in-flight-suspend.html > > * igt@gem > _persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive > : > - shard-hsw: [TIMEOUT][43] ([fdo#112068 ]) -> [PASS][44] > [43]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html > [44]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-hsw5/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html > > * igt@gem_ppgtt@flink-and-close-vma-leak: > - shard-kbl: [FAIL][45] ([fdo#112392]) -> [PASS][46] > [45]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-kbl4/igt@gem_ppgtt@flink-and-close-vma-leak.html > [46]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-kbl6/igt@gem_ppgtt@flink-and-close-vma-leak.html > > * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup: > - shard-snb: [DMESG-WARN][47] ([fdo#111870]) -> > [PASS][48] > [47]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html > [48]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html > > * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: > - shard-hsw: [DMESG-WARN][49] ([fdo#111870]) -> > [PASS][50] > [49]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-hsw4/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html > [50]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-hsw7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html > > * igt@gem_workarounds@suspend-resume-fd: > - shard-kbl: [DMESG-WARN][51] ([fdo#108566]) -> > [PASS][52] +5 similar issues > [51]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html > [52]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-kbl6/igt@gem_workarounds@suspend-resume-fd.html > > * igt@kms_color@pipe-a-ctm-0-75: > - shard-skl: [DMESG-WARN][53] ([fdo#106107]) -> > [PASS][54] > [53]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-skl4/igt@kms_color@pipe-a-ctm-0-75.html > [54]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-skl9/igt@kms_color@pipe-a-ctm-0-75.html > > * igt@kms_cursor_legacy@cursor-vs-flip-varying-size: > - shard-hsw: [FAIL][55] ([fdo#103355]) -> [PASS][56] > [55]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-hsw5/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html > [56]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-hsw5/igt@kms_cursor_legacy@cursor-vs-flip-varying-size.html > > * igt@kms_flip@flip-vs-suspend-interruptible: > - shard-apl: [DMESG-WARN][57] ([fdo#108566]) -> > [PASS][58] +1 similar issue > [57]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible.html > [58]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible.html > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move: > - shard-tglb: [INCOMPLETE][59] ([fdo#111884]) -> > [PASS][60] > [59]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move.html > [60]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move.html > > * igt@kms > _frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite: > - shard-iclb: [FAIL][61] ([fdo#103167]) -> [PASS][62] +1 > similar issue > [61]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html > [62]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html > > * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte: > - shard-tglb: [INCOMPLETE][63] ([fdo#111747] / > [fdo#111884]) -> [PASS][64] > [63]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html > [64]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html > > * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc: > - shard-tglb: [FAIL][65] ([fdo#103167]) -> [PASS][66] +2 > similar issues > [65]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html > [66]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html > > * igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary: > - shard-skl: [INCOMPLETE][67] ([fdo#106978]) -> > [PASS][68] > [67]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-skl6/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html > [68]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-skl7/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html > > * igt@kms_plane@pixel-format-pipe-b-planes: > - shard-kbl: [INCOMPLETE][69] ([fdo#103665]) -> > [PASS][70] +1 similar issue > [69]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-kbl4/igt@kms_plane@pixel-format-pipe-b-planes.html > [70]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-kbl6/igt@kms_plane@pixel-format-pipe-b-planes.html > > * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: > - shard-skl: [FAIL][71] ([fdo#108145] / [fdo#110403]) -> > [PASS][72] > [71]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html > [72]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html > > * igt@kms_setmode@basic: > - shard-apl: [FAIL][73] ([fdo#99912]) -> [PASS][74] > [73]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-apl4/igt@kms_setmode@basic.html > [74]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-apl7/igt@kms_setmode@basic.html > > > #### Warnings #### > > * igt@kms > _cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: > - shard-skl: [FAIL][75] ([fdo#102670]) -> [FAIL][76] > ([fdo#102670] / [fdo#106081]) > [75]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html > [76]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html > > > [fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670 > [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 > [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355 > [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 > [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540 > [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 > [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 > [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411 > [fdo#106081]: https://bugs.freedesktop.org/show_bug.cgi?id=106081 > [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107 > [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978 > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 > [fdo#108838]: https://bugs.freedesktop.org/show_bug.cgi?id=108838 > [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403 > [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789 > [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747 > [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832 > [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850 > [fdo#111867]: https://bugs.freedesktop.org/show_bug.cgi?id=111867 > [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870 > [fdo#111884]: https://bugs.freedesktop.org/show_bug.cgi?id=111884 > [fdo#112068 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112068 > [fdo#112081]: https://bugs.freedesktop.org/show_bug.cgi?id=112081 > [fdo#112347]: https://bugs.freedesktop.org/show_bug.cgi?id=112347 > [fdo#112392]: https://bugs.freedesktop.org/show_bug.cgi?id=112392 > [fdo#112409]: https://bugs.freedesktop.org/show_bug.cgi?id=112409 > [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 > [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 > > > Participating hosts (11 -> 11) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * CI: CI-20190529 -> None > * Linux: CI_DRM_7426 -> Patchwork_15450 > > CI-20190529: 20190529 > CI_DRM_7426: b204d72d3485a148456e2077683974739b675b21 @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_5310: d1ea62b3f759f10ff6860561ba82e5c4902511d3 @ > git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_15450: e9f140854637460868bc1c43d76cfde8cd03a4b7 @ > git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ > git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15450/index.html
On Tue, Nov 26, 2019 at 03:17:17PM -0800, José Roberto de Souza wrote: > Talked with HW team and this is a left over, driver should not > program clockgating, dekel firmware will be reponsible for any > clockgating programing. > > BSpec issue: 20885 > BSpec: 49292 > > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 55 +++++++----------------- > 1 file changed, 16 insertions(+), 39 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index a976606d21c7..7488dcbb637f 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3167,6 +3167,11 @@ icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable) > u32 val, bits; > int ln; > > + /* > + * Should not be called for GEN12+, see "PHY Clockgating programming" > + * note > + */ > + > if (tc_port == PORT_TC_NONE) > return; > > @@ -3175,39 +3180,26 @@ icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable) > MG_DP_MODE_CFG_GAONPWR_GATING; > > for (ln = 0; ln < 2; ln++) { > - if (INTEL_GEN(dev_priv) >= 12) { > - I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln)); > - val = I915_READ(DKL_DP_MODE(tc_port)); > - } else { > - val = I915_READ(MG_DP_MODE(ln, tc_port)); > - } > + val = I915_READ(MG_DP_MODE(ln, tc_port)); > > if (enable) > val |= bits; > else > val &= ~bits; > > - if (INTEL_GEN(dev_priv) >= 12) > - I915_WRITE(DKL_DP_MODE(tc_port), val); > - else > - I915_WRITE(MG_DP_MODE(ln, tc_port), val); > + I915_WRITE(MG_DP_MODE(ln, tc_port), val); > } > > - if (INTEL_GEN(dev_priv) == 11) { > - bits = MG_MISC_SUS0_CFG_TR2PWR_GATING | > - MG_MISC_SUS0_CFG_CL2PWR_GATING | > - MG_MISC_SUS0_CFG_GAONPWR_GATING | > - MG_MISC_SUS0_CFG_TRPWR_GATING | > - MG_MISC_SUS0_CFG_CL1PWR_GATING | > - MG_MISC_SUS0_CFG_DGPWR_GATING; > + bits = MG_MISC_SUS0_CFG_TR2PWR_GATING | MG_MISC_SUS0_CFG_CL2PWR_GATING | > + MG_MISC_SUS0_CFG_GAONPWR_GATING | MG_MISC_SUS0_CFG_TRPWR_GATING | > + MG_MISC_SUS0_CFG_CL1PWR_GATING | MG_MISC_SUS0_CFG_DGPWR_GATING; > > - val = I915_READ(MG_MISC_SUS0(tc_port)); > - if (enable) > - val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3)); > - else > - val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK); > - I915_WRITE(MG_MISC_SUS0(tc_port), val); > - } > + val = I915_READ(MG_MISC_SUS0(tc_port)); > + if (enable) > + val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3)); > + else > + val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK); > + I915_WRITE(MG_MISC_SUS0(tc_port), val); > } > > static void > @@ -3508,12 +3500,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, > * down this function. > */ > > - /* > - * 7.d Type C with DP alternate or fixed/legacy/static connection - > - * Disable PHY clock gating per Type-C DDI Buffer page > - */ > - icl_phy_set_clock_gating(dig_port, false); > - > /* 7.e Configure voltage swing and related IO settings */ > tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level, > encoder->type); > @@ -3565,15 +3551,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, > if (!is_trans_port_sync_mode(crtc_state)) > intel_dp_stop_link_train(intel_dp); > > - /* > - * TODO: enable clock gating > - * > - * It is not written in DP enabling sequence but "PHY Clockgating > - * programming" states that clock gating should be enabled after the > - * link training but doing so causes all the following trainings to fail > - * so not enabling it for now. > - */ > - > /* 7.l Configure and enable FEC if needed */ > intel_ddi_enable_fec(encoder, crtc_state); > intel_dsc_enable(encoder, crtc_state); > -- > 2.24.0 >
On Tue, 26 Nov 2019, José Roberto de Souza <jose.souza@intel.com> wrote: > Talked with HW team and this is a left over, driver should not > program clockgating, dekel firmware will be reponsible for any > clockgating programing. > > BSpec issue: 20885 > BSpec: 49292 > > Cc: Lucas De Marchi <lucas.demarchi@intel.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 55 +++++++----------------- > 1 file changed, 16 insertions(+), 39 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index a976606d21c7..7488dcbb637f 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -3167,6 +3167,11 @@ icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable) > u32 val, bits; > int ln; > > + /* > + * Should not be called for GEN12+, see "PHY Clockgating programming" > + * note > + */ > + IMHO this kind of comments do us no good. If you want to be paranoid, if (WARN_ON(INTEL_GEN(dev_priv) >= 12)) return; which has the benefit of being self-documenting code. But I'm not convinced of even that. BR, Jani. > if (tc_port == PORT_TC_NONE) > return; > > @@ -3175,39 +3180,26 @@ icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable) > MG_DP_MODE_CFG_GAONPWR_GATING; > > for (ln = 0; ln < 2; ln++) { > - if (INTEL_GEN(dev_priv) >= 12) { > - I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln)); > - val = I915_READ(DKL_DP_MODE(tc_port)); > - } else { > - val = I915_READ(MG_DP_MODE(ln, tc_port)); > - } > + val = I915_READ(MG_DP_MODE(ln, tc_port)); > > if (enable) > val |= bits; > else > val &= ~bits; > > - if (INTEL_GEN(dev_priv) >= 12) > - I915_WRITE(DKL_DP_MODE(tc_port), val); > - else > - I915_WRITE(MG_DP_MODE(ln, tc_port), val); > + I915_WRITE(MG_DP_MODE(ln, tc_port), val); > } > > - if (INTEL_GEN(dev_priv) == 11) { > - bits = MG_MISC_SUS0_CFG_TR2PWR_GATING | > - MG_MISC_SUS0_CFG_CL2PWR_GATING | > - MG_MISC_SUS0_CFG_GAONPWR_GATING | > - MG_MISC_SUS0_CFG_TRPWR_GATING | > - MG_MISC_SUS0_CFG_CL1PWR_GATING | > - MG_MISC_SUS0_CFG_DGPWR_GATING; > + bits = MG_MISC_SUS0_CFG_TR2PWR_GATING | MG_MISC_SUS0_CFG_CL2PWR_GATING | > + MG_MISC_SUS0_CFG_GAONPWR_GATING | MG_MISC_SUS0_CFG_TRPWR_GATING | > + MG_MISC_SUS0_CFG_CL1PWR_GATING | MG_MISC_SUS0_CFG_DGPWR_GATING; > > - val = I915_READ(MG_MISC_SUS0(tc_port)); > - if (enable) > - val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3)); > - else > - val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK); > - I915_WRITE(MG_MISC_SUS0(tc_port), val); > - } > + val = I915_READ(MG_MISC_SUS0(tc_port)); > + if (enable) > + val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3)); > + else > + val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK); > + I915_WRITE(MG_MISC_SUS0(tc_port), val); > } > > static void > @@ -3508,12 +3500,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, > * down this function. > */ > > - /* > - * 7.d Type C with DP alternate or fixed/legacy/static connection - > - * Disable PHY clock gating per Type-C DDI Buffer page > - */ > - icl_phy_set_clock_gating(dig_port, false); > - > /* 7.e Configure voltage swing and related IO settings */ > tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level, > encoder->type); > @@ -3565,15 +3551,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, > if (!is_trans_port_sync_mode(crtc_state)) > intel_dp_stop_link_train(intel_dp); > > - /* > - * TODO: enable clock gating > - * > - * It is not written in DP enabling sequence but "PHY Clockgating > - * programming" states that clock gating should be enabled after the > - * link training but doing so causes all the following trainings to fail > - * so not enabling it for now. > - */ > - > /* 7.l Configure and enable FEC if needed */ > intel_ddi_enable_fec(encoder, crtc_state); > intel_dsc_enable(encoder, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index a976606d21c7..7488dcbb637f 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3167,6 +3167,11 @@ icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable) u32 val, bits; int ln; + /* + * Should not be called for GEN12+, see "PHY Clockgating programming" + * note + */ + if (tc_port == PORT_TC_NONE) return; @@ -3175,39 +3180,26 @@ icl_phy_set_clock_gating(struct intel_digital_port *dig_port, bool enable) MG_DP_MODE_CFG_GAONPWR_GATING; for (ln = 0; ln < 2; ln++) { - if (INTEL_GEN(dev_priv) >= 12) { - I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln)); - val = I915_READ(DKL_DP_MODE(tc_port)); - } else { - val = I915_READ(MG_DP_MODE(ln, tc_port)); - } + val = I915_READ(MG_DP_MODE(ln, tc_port)); if (enable) val |= bits; else val &= ~bits; - if (INTEL_GEN(dev_priv) >= 12) - I915_WRITE(DKL_DP_MODE(tc_port), val); - else - I915_WRITE(MG_DP_MODE(ln, tc_port), val); + I915_WRITE(MG_DP_MODE(ln, tc_port), val); } - if (INTEL_GEN(dev_priv) == 11) { - bits = MG_MISC_SUS0_CFG_TR2PWR_GATING | - MG_MISC_SUS0_CFG_CL2PWR_GATING | - MG_MISC_SUS0_CFG_GAONPWR_GATING | - MG_MISC_SUS0_CFG_TRPWR_GATING | - MG_MISC_SUS0_CFG_CL1PWR_GATING | - MG_MISC_SUS0_CFG_DGPWR_GATING; + bits = MG_MISC_SUS0_CFG_TR2PWR_GATING | MG_MISC_SUS0_CFG_CL2PWR_GATING | + MG_MISC_SUS0_CFG_GAONPWR_GATING | MG_MISC_SUS0_CFG_TRPWR_GATING | + MG_MISC_SUS0_CFG_CL1PWR_GATING | MG_MISC_SUS0_CFG_DGPWR_GATING; - val = I915_READ(MG_MISC_SUS0(tc_port)); - if (enable) - val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3)); - else - val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK); - I915_WRITE(MG_MISC_SUS0(tc_port), val); - } + val = I915_READ(MG_MISC_SUS0(tc_port)); + if (enable) + val |= (bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3)); + else + val &= ~(bits | MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK); + I915_WRITE(MG_MISC_SUS0(tc_port), val); } static void @@ -3508,12 +3500,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, * down this function. */ - /* - * 7.d Type C with DP alternate or fixed/legacy/static connection - - * Disable PHY clock gating per Type-C DDI Buffer page - */ - icl_phy_set_clock_gating(dig_port, false); - /* 7.e Configure voltage swing and related IO settings */ tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level, encoder->type); @@ -3565,15 +3551,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, if (!is_trans_port_sync_mode(crtc_state)) intel_dp_stop_link_train(intel_dp); - /* - * TODO: enable clock gating - * - * It is not written in DP enabling sequence but "PHY Clockgating - * programming" states that clock gating should be enabled after the - * link training but doing so causes all the following trainings to fail - * so not enabling it for now. - */ - /* 7.l Configure and enable FEC if needed */ intel_ddi_enable_fec(encoder, crtc_state); intel_dsc_enable(encoder, crtc_state);
Talked with HW team and this is a left over, driver should not program clockgating, dekel firmware will be reponsible for any clockgating programing. BSpec issue: 20885 BSpec: 49292 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 55 +++++++----------------- 1 file changed, 16 insertions(+), 39 deletions(-)