diff mbox series

[v6,4/7] ARM: dts: sun8i-h3: Add thermal sensor and thermal zones

Message ID 20191127052935.1719897-5-anarsoul@gmail.com (mailing list archive)
State New, archived
Delegated to: Eduardo Valentin
Headers show
Series add thermal sensor driver for A64, A83T, H3, H5, H6, R40 | expand

Commit Message

Vasily Khoruzhick Nov. 27, 2019, 5:29 a.m. UTC
From: Ondrej Jirman <megous@megous.com>

There is just one sensor for the CPU.

Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

Comments

Samuel Holland Nov. 27, 2019, 7:40 p.m. UTC | #1
Hi,

On 11/26/19 11:29 PM, Vasily Khoruzhick wrote:
> From: Ondrej Jirman <megous@megous.com>
> 
> There is just one sensor for the CPU.
> 
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> ---
>  arch/arm/boot/dts/sun8i-h3.dtsi | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index e37c30e811d3..42fd0418d678 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -177,6 +177,26 @@
>  			assigned-clocks = <&ccu CLK_GPU>;
>  			assigned-clock-rates = <384000000>;
>  		};
> +
> +		ths: ths@1c25000 {
> +			compatible = "allwinner,sun8i-h3-ths";
> +			reg = <0x01c25000 0x400>;
> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +			resets = <&ccu RST_BUS_THS>;
> +			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
> +			clock-names = "bus", "mod";
> +			nvmem-cells = <&ths_calibration>;
> +			nvmem-cell-names = "calibration";
> +			#thermal-sensor-cells = <0>;
> +		};
> +	};
> +
> +	thermal-zones {
> +		cpu_thermal: cpu-thermal {
> +			polling-delay-passive = <0>;
> +			polling-delay = <0>;
> +			thermal-sensors = <&ths 0>;
> +		};
>  	};
>  };
>  
> @@ -234,4 +254,10 @@
>  
>  &sid {
>  	compatible = "allwinner,sun8i-h3-sid";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	ths_calibration: thermal-sensor-calibration@34 {
> +		reg = <0x34 4>;
> +	};

All of the lines added here are common between the H3 and H5, so they can go in
the shared SID node in sunxi-h3-h5.dtsi.

Cheers,
Samuel

>  };
>
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index e37c30e811d3..42fd0418d678 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -177,6 +177,26 @@ 
 			assigned-clocks = <&ccu CLK_GPU>;
 			assigned-clock-rates = <384000000>;
 		};
+
+		ths: ths@1c25000 {
+			compatible = "allwinner,sun8i-h3-ths";
+			reg = <0x01c25000 0x400>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&ccu RST_BUS_THS>;
+			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+			clock-names = "bus", "mod";
+			nvmem-cells = <&ths_calibration>;
+			nvmem-cell-names = "calibration";
+			#thermal-sensor-cells = <0>;
+		};
+	};
+
+	thermal-zones {
+		cpu_thermal: cpu-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&ths 0>;
+		};
 	};
 };
 
@@ -234,4 +254,10 @@ 
 
 &sid {
 	compatible = "allwinner,sun8i-h3-sid";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	ths_calibration: thermal-sensor-calibration@34 {
+		reg = <0x34 4>;
+	};
 };