| Message ID | 20191128155515.19013-1-drjones@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [kvm-unit-tests] arm/arm64: PL031: Fix check_rtc_irq | expand |
On Thu, Nov 28, 2019 at 04:55:15PM +0100, Andrew Jones wrote: > Since QEMU commit 83ad95957c7e ("pl031: Expose RTCICR as proper WC > register") the PL031 test gets into an infinite loop. Now we must > write bit zero of RTCICR to clear the IRQ status. Before, writing > anything to RTCICR would work. As '1' is a member of 'anything' > writing it should work for old QEMU as well. > > Cc: Alexander Graf <graf@amazon.com> > Signed-off-by: Andrew Jones <drjones@redhat.com> > --- > arm/pl031.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Note, this is based on not yet merged "Switch the order of the parameters in report() and report_xfail()". > > diff --git a/arm/pl031.c b/arm/pl031.c > index 1f63ef13994f..3b75fd653e96 100644 > --- a/arm/pl031.c > +++ b/arm/pl031.c > @@ -143,8 +143,8 @@ static void irq_handler(struct pt_regs *regs) > report(readl(&pl031->ris) == 1, " RTC RIS == 1"); > report(readl(&pl031->mis) == 1, " RTC MIS == 1"); > > - /* Writing any value should clear IRQ status */ > - writel(0x80000000ULL, &pl031->icr); > + /* Writing one to bit zero should clear IRQ status */ > + writel(1, &pl031->icr); > > report(readl(&pl031->ris) == 0, " RTC RIS == 0"); > report(readl(&pl031->mis) == 0, " RTC MIS == 0"); > -- > 2.21.0 >
> Am 28.11.2019 um 17:56 schrieb "drjones@redhat.com" <drjones@redhat.com>: > > Since QEMU commit 83ad95957c7e ("pl031: Expose RTCICR as proper WC > register") the PL031 test gets into an infinite loop. Now we must > write bit zero of RTCICR to clear the IRQ status. Before, writing > anything to RTCICR would work. As '1' is a member of 'anything' > writing it should work for old QEMU as well. > > Cc: Alexander Graf <graf@amazon.com> > Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Alexander Graf <graf@amazon.com> Sorry for introducing a test case on code that I then modify, without updating the test case as well :) Alex > --- > arm/pl031.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arm/pl031.c b/arm/pl031.c > index 1f63ef13994f..3b75fd653e96 100644 > --- a/arm/pl031.c > +++ b/arm/pl031.c > @@ -143,8 +143,8 @@ static void irq_handler(struct pt_regs *regs) > report(readl(&pl031->ris) == 1, " RTC RIS == 1"); > report(readl(&pl031->mis) == 1, " RTC MIS == 1"); > > - /* Writing any value should clear IRQ status */ > - writel(0x80000000ULL, &pl031->icr); > + /* Writing one to bit zero should clear IRQ status */ > + writel(1, &pl031->icr); > > report(readl(&pl031->ris) == 0, " RTC RIS == 0"); > report(readl(&pl031->mis) == 0, " RTC MIS == 0"); > -- > 2.21.0 > Amazon Development Center Germany GmbH Krausenstr. 38 10117 Berlin Geschaeftsfuehrung: Christian Schlaeger, Ralf Herbrich Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B Sitz: Berlin Ust-ID: DE 289 237 879
diff --git a/arm/pl031.c b/arm/pl031.c index 1f63ef13994f..3b75fd653e96 100644 --- a/arm/pl031.c +++ b/arm/pl031.c @@ -143,8 +143,8 @@ static void irq_handler(struct pt_regs *regs) report(readl(&pl031->ris) == 1, " RTC RIS == 1"); report(readl(&pl031->mis) == 1, " RTC MIS == 1"); - /* Writing any value should clear IRQ status */ - writel(0x80000000ULL, &pl031->icr); + /* Writing one to bit zero should clear IRQ status */ + writel(1, &pl031->icr); report(readl(&pl031->ris) == 0, " RTC RIS == 0"); report(readl(&pl031->mis) == 0, " RTC MIS == 0");
Since QEMU commit 83ad95957c7e ("pl031: Expose RTCICR as proper WC register") the PL031 test gets into an infinite loop. Now we must write bit zero of RTCICR to clear the IRQ status. Before, writing anything to RTCICR would work. As '1' is a member of 'anything' writing it should work for old QEMU as well. Cc: Alexander Graf <graf@amazon.com> Signed-off-by: Andrew Jones <drjones@redhat.com> --- arm/pl031.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)