@@ -149,8 +149,8 @@ static void irq_handler(struct pt_regs *regs)
u32 irqstat = gic_read_iar();
u32 irqnr = gic_iar_irqnr(irqstat);
- if (irqnr != GICC_INT_SPURIOUS)
- gic_write_eoir(irqstat);
+ if (irqnr == GICC_INT_SPURIOUS)
+ return;
if (irqnr == PPI(vtimer_info.irq)) {
info = &vtimer_info;
@@ -162,7 +162,11 @@ static void irq_handler(struct pt_regs *regs)
}
info->write_ctl(ARCH_TIMER_CTL_IMASK | ARCH_TIMER_CTL_ENABLE);
+ isb();
+
info->irq_received = true;
+
+ gic_write_eoir(irqstat);
}
static bool gic_timer_pending(struct timer_info *info)
Writing to the EOIR register before masking the HW mapped timer interrupt can cause taking another timer interrupt immediately after exception return. This doesn't happen all the time, because KVM reevaluates the state of pending HW mapped level sensitive interrupts on each guest exit. If the second interrupt is pending and a guest exit occurs after masking the timer interrupt and before the ERET (which restores PSTATE.I), then KVM removes it. Move the write after the IMASK bit has been set to prevent this from happening. Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> --- arm/timer.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)