From patchwork Fri Nov 29 14:45:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jian Hu X-Patchwork-Id: 11267251 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5CB39921 for ; Fri, 29 Nov 2019 14:47:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0A502217AB for ; Fri, 29 Nov 2019 14:47:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="rbP5/rTV" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0A502217AB Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amlogic.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2Flq5zSc3N3GyxDTqk0RjssvRvVw2ldu+zZN+3ak324=; b=rbP5/rTVu3KU6X 4TmebuFrM668z4zJQYfCLYTMMLrsOr6MYVUv5LDKHavM3dLKArLjL+SQJSNo2g5ip38PvINXDkSnd 6wPmz5x60QicdZNNOe1VPOf4MzTlabojJrvEvXY5CwlEKktfc6WeyfAULDw8pNZsCFMiaDFIf7fIq 7ZHUCBLIHFwJcAioT1auGGWcgrLWMV0c1BFhlm3PfTLln1NkqKL77lmyuX/mG23CuAdY3ORC1Xjo8 /mC4lq5wdmC5xsodvym0hjufrh4kVFbj8LMzz6VXiJY35V+uwuZ6I0CYda5iINTzrWQ3IZnazxnb/ PfnzDaKgwdfTSqBfqomg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iahY5-0004Cm-Ai; Fri, 29 Nov 2019 14:47:09 +0000 Received: from mail-sz.amlogic.com ([211.162.65.117]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iahXb-0003gZ-6m; Fri, 29 Nov 2019 14:46:44 +0000 Received: from droid15-sz.amlogic.com (10.28.8.25) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.1591.10; Fri, 29 Nov 2019 22:46:36 +0800 From: Jian Hu To: Jerome Brunet , Neil Armstrong Subject: [PATCH v3 1/7] dt-bindings: clock: meson: add A1 PLL clock controller bindings Date: Fri, 29 Nov 2019 22:45:59 +0800 Message-ID: <20191129144605.182774-2-jian.hu@amlogic.com> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191129144605.182774-1-jian.hu@amlogic.com> References: <20191129144605.182774-1-jian.hu@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.8.25] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191129_064640_382830_D43FB5E0 X-CRM114-Status: UNSURE ( 9.38 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Victor Wan , Jianxin Pan , devicetree@vger.kernel.org, Martin Blumenstingl , Kevin Hilman , Michael Turquette , linux-kernel@vger.kernel.org, Stephen Boyd , Jian Hu , linux-arm-kernel@lists.infradead.org, Qiufang Dai , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, Chandle Zou Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org Add the documentation to support Amlogic A1 PLL clock driver, and add A1 PLL clock controller bindings. Signed-off-by: Jian Hu --- .../bindings/clock/amlogic,a1-pll-clkc.yaml | 56 +++++++++++++++++++ include/dt-bindings/clock/a1-pll-clkc.h | 16 ++++++ 2 files changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml new file mode 100644 index 000000000000..d008bfeb3c3a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson A/C serials PLL Clock Control Unit Device Tree Bindings + +maintainers: + - Neil Armstrong + - Jerome Brunet + - Jian Hu + +properties: + compatible: + - enum: + - amlogic,a1-pll-clkc + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +clocks: + minItems: 2 + maxItems: 2 + items: + - description: Input xtal_fixpll + - description: Input xtal_hifipll + +clock-names: + minItems: 2 + maxItems: 2 + items: + - const: xtal_fixpll + - const: xtal_hifipll + +required: + - compatible + - "#clock-cells" + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + clkc_pll: pll-clock-controller { + compatible = "amlogic,a1-pll-clkc"; + reg = <0 0x7c80 0 0x18c>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/a1-pll-clkc.h b/include/dt-bindings/clock/a1-pll-clkc.h new file mode 100644 index 000000000000..58eae237e503 --- /dev/null +++ b/include/dt-bindings/clock/a1-pll-clkc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#ifndef __A1_PLL_CLKC_H +#define __A1_PLL_CLKC_H + +#define CLKID_FIXED_PLL 1 +#define CLKID_FCLK_DIV2 6 +#define CLKID_FCLK_DIV3 7 +#define CLKID_FCLK_DIV5 8 +#define CLKID_FCLK_DIV7 9 +#define CLKID_HIFI_PLL 10 + +#endif /* __A1_PLL_CLKC_H */