diff mbox series

[RESEND] clk: imx6q: disable non functional divider

Message ID 20191202134119.194625-1-j.remmet@phytec.de (mailing list archive)
State Mainlined
Commit 3ff86050da41e072dd9fffc373c4f5691573cf4e
Headers show
Series [RESEND] clk: imx6q: disable non functional divider | expand

Commit Message

Jan Remmet Dec. 2, 2019, 1:41 p.m. UTC 
The /2 divider between pll4_audio_div and pll4_post_div is not working
on imx6q. The frequency is not halved as reported by the clock tree
and measured on clko.
In the technical reference manual the divider was removed in revision 4.
It's also not listed in the imx6qp manual.

imx6dl manual mentions a divider for PLL4 and the according register
description. So keep the divider here.

Signed-off-by: Jan Remmet <j.remmet@phytec.de>
---
 drivers/clk/imx/clk-imx6q.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Comments

Shawn Guo Dec. 9, 2019, 2:09 a.m. UTC | #1 
On Mon, Dec 02, 2019 at 02:41:19PM +0100, Jan Remmet wrote:
> The /2 divider between pll4_audio_div and pll4_post_div is not working
> on imx6q. The frequency is not halved as reported by the clock tree
> and measured on clko.
> In the technical reference manual the divider was removed in revision 4.
> It's also not listed in the imx6qp manual.
> 
> imx6dl manual mentions a divider for PLL4 and the according register
> description. So keep the divider here.
> 
> Signed-off-by: Jan Remmet <j.remmet@phytec.de>

Applied, thanks.
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 60f2de851f39..ba33c79158de 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -598,7 +598,10 @@  static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	}
 
 	hws[IMX6QDL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
-	hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
+	if (clk_on_imx6q() || clk_on_imx6qp())
+		hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = imx_clk_hw_fixed_factor("pll4_audio_div", "pll4_post_div", 1, 1);
+	else
+		hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
 	hws[IMX6QDL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
 	hws[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);