arm64: dts: a1: add saradc controller
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Message ID 1575358332-44866-1-git-send-email-xingyu.chen@amlogic.com
State New
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  • arm64: dts: a1: add saradc controller
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Commit Message

Xingyu Chen Dec. 3, 2019, 7:32 a.m. UTC
The saradc controller in Meson-A1 is the same as the Meson-G12 series SoCs,
so we use the same compatible string.

Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>

---
This patch is based on A1 clock patchset at [0].

[0] https://lore.kernel.org/linux-amlogic/20191129144605.182774-1-jian.hu@amlogic.com
---
 arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Comments

Kevin Hilman Dec. 9, 2019, 10:56 p.m. UTC | #1
Xingyu Chen <xingyu.chen@amlogic.com> writes:

> The saradc controller in Meson-A1 is the same as the Meson-G12 series SoCs,
> so we use the same compatible string.
>
> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
>
> ---
> This patch is based on A1 clock patchset at [0].
>
> [0] https://lore.kernel.org/linux-amlogic/20191129144605.182774-1-jian.hu@amlogic.com
> ---
>  arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> index 7210ad0..cad1756 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> @@ -93,6 +93,21 @@
>  				clock-names = "xtal", "pclk", "baud";
>  				status = "disabled";
>  			};
> +
> +			saradc: adc@2c00 {
> +				compatible = "amlogic,meson-g12a-saradc",
> +					     "amlogic,meson-saradc";
> +				reg = <0x0 0x2c00 0x0 0x48>;

Why 0x48 here?  AXG uses 0x38 and you're not adding any more registers
to this driver.

Kevin
Xingyu Chen Dec. 10, 2019, 3:57 a.m. UTC | #2
Hi, Kevin

On 2019/12/10 6:56, Kevin Hilman wrote:
> Xingyu Chen <xingyu.chen@amlogic.com> writes:
>
>> The saradc controller in Meson-A1 is the same as the Meson-G12 series SoCs,
>> so we use the same compatible string.
>>
>> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
>>
>> ---
>> This patch is based on A1 clock patchset at [0].
>>
>> [0] https://lore.kernel.org/linux-amlogic/20191129144605.182774-1-jian.hu@amlogic.com
>> ---
>>   arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 15 +++++++++++++++
>>   1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> index 7210ad0..cad1756 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> @@ -93,6 +93,21 @@
>>   				clock-names = "xtal", "pclk", "baud";
>>   				status = "disabled";
>>   			};
>> +
>> +			saradc: adc@2c00 {
>> +				compatible = "amlogic,meson-g12a-saradc",
>> +					     "amlogic,meson-saradc";
>> +				reg = <0x0 0x2c00 0x0 0x48>;
> Why 0x48 here?  AXG uses 0x38 and you're not adding any more registers
> to this driver.

Thanks for you review.

The saradc introduces 4 new registers (as shown below) begin with g12a 
platform, and these registers are used
to save the sampling value of corresponding channel. In other words, we 
can choose fifo or new registers to save
sampling value, but it is not supported by the current driver.

dout register  |---> fifo
                          |---> channel regs -|
                                                            |--- channel-0
                                                            |--- channel-1
                                                            | ...
                                                            | --- channel-7

AO_SAR_ADC_CHNL01:saving sampling data of channel 0/1
AO_SAR_ADC_CHNL23:   saving sampling data of channel 2/3
AO_SAR_ADC_CHNL45:   saving sampling data of channel 4/5
AO_SAR_ADC_CHNL67:   saving sampling data of channel 6/7


This patch use the 0x48 to describe the registers length just follow the 
file meson-g12-common.dtsi. and it doesn't
affect the driver because of the mapped regiter length is limited by 
max_register member in struct regmap_config.

I can replace 0x48 with 0x38 in next patch if necessary.

> Kevin
>
> .
>
Kevin Hilman Dec. 10, 2019, 6:41 p.m. UTC | #3
Xingyu Chen <xingyu.chen@amlogic.com> writes:

> Hi, Kevin
>
> On 2019/12/10 6:56, Kevin Hilman wrote:
>> Xingyu Chen <xingyu.chen@amlogic.com> writes:
>>
>>> The saradc controller in Meson-A1 is the same as the Meson-G12 series SoCs,
>>> so we use the same compatible string.
>>>
>>> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
>>>
>>> ---
>>> This patch is based on A1 clock patchset at [0].
>>>
>>> [0] https://lore.kernel.org/linux-amlogic/20191129144605.182774-1-jian.hu@amlogic.com
>>> ---
>>>   arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 15 +++++++++++++++
>>>   1 file changed, 15 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>>> index 7210ad0..cad1756 100644
>>> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>>> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>>> @@ -93,6 +93,21 @@
>>>   				clock-names = "xtal", "pclk", "baud";
>>>   				status = "disabled";
>>>   			};
>>> +
>>> +			saradc: adc@2c00 {
>>> +				compatible = "amlogic,meson-g12a-saradc",
>>> +					     "amlogic,meson-saradc";
>>> +				reg = <0x0 0x2c00 0x0 0x48>;
>> Why 0x48 here?  AXG uses 0x38 and you're not adding any more registers
>> to this driver.
>
> Thanks for you review.
>
> The saradc introduces 4 new registers (as shown below) begin with g12a 
> platform, and these registers are used
> to save the sampling value of corresponding channel. In other words, we 
> can choose fifo or new registers to save
> sampling value, but it is not supported by the current driver.
>
> dout register  |---> fifo
>                           |---> channel regs -|
>                                                             |--- channel-0
>                                                             |--- channel-1
>                                                             | ...
>                                                             | --- channel-7
>
> AO_SAR_ADC_CHNL01:saving sampling data of channel 0/1
> AO_SAR_ADC_CHNL23:   saving sampling data of channel 2/3
> AO_SAR_ADC_CHNL45:   saving sampling data of channel 4/5
> AO_SAR_ADC_CHNL67:   saving sampling data of channel 6/7

I understand there are new registers in the hardware, but I don't think
the current driver is using those.  Please correct me if I'm wrong.

> This patch use the 0x48 to describe the registers length just follow the 
> file meson-g12-common.dtsi.

OK, my fault. I was comparing with AXG instead of G12A.  But still, if
the driver is not using those registers, then g12 DT files are wrong too.

That being said, I'm not going to be too picky about that.  

> and it doesn't affect the driver because of the mapped regiter length
> is limited by max_register member in struct regmap_config.
>
> I can replace 0x48 with 0x38 in next patch if necessary.

Since G12 is already using 0x48 and this device is compatible with G12,
I'm fine leaving it at 0x48.

Thanks,

Kevin

Patch
diff mbox series

diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..cad1756 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -93,6 +93,21 @@ 
 				clock-names = "xtal", "pclk", "baud";
 				status = "disabled";
 			};
+
+			saradc: adc@2c00 {
+				compatible = "amlogic,meson-g12a-saradc",
+					     "amlogic,meson-saradc";
+				reg = <0x0 0x2c00 0x0 0x48>;
+				#io-channel-cells = <1>;
+				interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>,
+					 <&clkc_periphs CLKID_SARADC>,
+					 <&clkc_periphs CLKID_SARADC_CLK>,
+					 <&clkc_periphs CLKID_SARADC_SEL>;
+				clock-names = "clkin", "core", "adc_clk",
+					      "adc_sel";
+				status = "disabled";
+			};
 		};
 
 		gic: interrupt-controller@ff901000 {