From patchwork Tue Dec 3 14:35:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lipski, Mikita" X-Patchwork-Id: 11271409 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F0FE914B7 for ; Tue, 3 Dec 2019 14:35:50 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D94E620659 for ; Tue, 3 Dec 2019 14:35:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D94E620659 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amd.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1B1A16E791; Tue, 3 Dec 2019 14:35:45 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-eopbgr770040.outbound.protection.outlook.com [40.107.77.40]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8B84C6E78E; Tue, 3 Dec 2019 14:35:43 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=c6PVsv5drPkFqECb4s6jG5GBkk70Wd4sLunlXcJG+hY270mUxkwh7NBJvqTJADn2ni4j8Efl2qfMdns1lox6KPIi/1BdrCWU3DAeG6HJdbjuJxgSUuTmc32P04zWVVrRiNY1ELC9bd9gWp1HKeE1VWv5szb7//op6p1Ur7MqolFXlOEteYb2/YMXqPFq9SLCRzAKT8qbu0Hse6oXwW/KRalNy/fH8uC1EVla7aVXrMYT9JQJakbsjxbtUP4B8+0JbcTQ0vpJMXk6IE/zmEzvOttr5IPsGZXRiaATS5XmzU7SyhMb5ajOohlIN5VVjWWNBV9UUHNMcixKRD9AYqTnLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ADDs09VYu6RtqHHO6cQB3J89YqLR85G9vZWlYjPo22s=; b=hEMbUcU8J7fLd3Gs+d2BM8RbAlEVRQid7dZeM6/1reLfZ41+7U3jDhTKpl/UTkHPUCg9897PJWtZBgCe51jQ8W9alkCRxEAQsYV8iilOHVs33inKl0kPGn8+gL4CcXgDrXXoJ1KZ3dEivIdF3wcMmM/rzobEPyE+/DjVaT2gzQ1gg2DTRiyVkNNpltcZTqTe+vhgLmavvRVPMh0Q3xJ7+xkfCKL/I/mTNuGCLYdcW62aLBKNZrweRizdJqE2C9lVXe8BziEQUy6WGfZntlt8F+gY8oPNispEZjmW/y3hQq8v0IaTgdOJshHDY0PR3BA0dbOkpz8wjcsW1ud8z+UVfA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=none (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.freedesktop.org smtp.mailfrom=amd.com; dmarc=permerror action=none header.from=amd.com; dkim=none (message not signed); arc=none Received: from DM6PR12CA0022.namprd12.prod.outlook.com (2603:10b6:5:1c0::35) by BY5PR12MB4194.namprd12.prod.outlook.com (2603:10b6:a03:210::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2495.17; Tue, 3 Dec 2019 14:35:42 +0000 Received: from DM6NAM11FT054.eop-nam11.prod.protection.outlook.com (2a01:111:f400:7eaa::201) by DM6PR12CA0022.outlook.office365.com (2603:10b6:5:1c0::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2495.18 via Frontend Transport; Tue, 3 Dec 2019 14:35:42 +0000 Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Received: from SATLEXMB02.amd.com (165.204.84.17) by DM6NAM11FT054.mail.protection.outlook.com (10.13.173.95) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.2451.23 via Frontend Transport; Tue, 3 Dec 2019 14:35:42 +0000 Received: from SATLEXMB01.amd.com (10.181.40.142) by SATLEXMB02.amd.com (10.181.40.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 3 Dec 2019 08:35:41 -0600 Received: from mlipski-pc.amd.com (10.180.168.240) by SATLEXMB01.amd.com (10.181.40.142) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Tue, 3 Dec 2019 08:35:41 -0600 From: To: Subject: [PATCH v8 01/17] drm/dp_mst: Add PBN calculation for DSC modes Date: Tue, 3 Dec 2019 09:35:14 -0500 Message-ID: <20191203143530.27262-2-mikita.lipski@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203143530.27262-1-mikita.lipski@amd.com> References: <20191203143530.27262-1-mikita.lipski@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:165.204.84.17; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(396003)(39860400002)(346002)(136003)(376002)(428003)(189003)(199004)(2351001)(6916009)(26005)(7696005)(76176011)(51416003)(50466002)(426003)(81156014)(356004)(8676002)(11346002)(48376002)(2616005)(336012)(446003)(6666004)(1076003)(4326008)(81166006)(50226002)(186003)(478600001)(8936002)(70206006)(5660300002)(54906003)(86362001)(305945005)(70586007)(36756003)(2906002)(53416004)(316002)(2876002)(16586007)(16060500001); DIR:OUT; SFP:1101; SCL:1; SRVR:BY5PR12MB4194; H:SATLEXMB02.amd.com; FPR:; SPF:None; LANG:en; PTR:InfoDomainNonexistent; MX:1; A:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c8430b34-416f-4332-8bf3-08d777fe131b X-MS-TrafficTypeDiagnostic: BY5PR12MB4194: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-Forefront-PRVS: 02408926C4 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Zqg/Ky1oVMYb6UUFn0ReuAx8QUKPXWnzCG+E7WvwtXWH8Qd3TT0xBJ1WcYumyNlkopvGRhRGLPr0vh8m7ym5MIASdYUPB9+JpKN7JRR3Q72YCsyBD5IWVWfYUDwjWx6p5+CSMmTUUYivg034+NJEkLZmbDaFtrdaElfbcjdNzdx1XvjQoXZxln6+H+FIMo5sbPvSAs0bQD38AyP+Ey9vsPrNLH1XT3/5kkfd6ju3Pbj67OclgjT6pk8A3fYNV71kfBeW1BB+OtergTZGz6uKIXLqmbjNX1CgUj+fkhcTNApwvjcg5Vkrw16ZQKolEw/8M3ebnj6yJbwyqheoOUVCiW1+nG0UgPvXBOQDx+5AhpQxfeij2H8zcRfmJ/z/Sbn8DI3WNc6K/feN9gkLHIN53AKW9MV76Rk3xGclqJlKn9FvZyZ9lZzK7V370o6OA6PS X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Dec 2019 14:35:42.1347 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c8430b34-416f-4332-8bf3-08d777fe131b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4194 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ADDs09VYu6RtqHHO6cQB3J89YqLR85G9vZWlYjPo22s=; b=iHGEvBW7EUqA1IZxeATdqwm4BN9oiKZq69iIOHioNLd1l+RhfUVwcd7f1diM4SWuET0e3N8j2aE8YAPooqQcv203wKShl07uxEb0naHFh7V1Lqn5AAm3R9Gi+DJ2LTES7VWHxD6fn1ctQi/H4OCVrtrS66VP2Z9C8YyaPglMOuY= X-Mailman-Original-Authentication-Results: spf=none (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; lists.freedesktop.org; dkim=none (message not signed) header.d=none;lists.freedesktop.org; dmarc=permerror action=none header.from=amd.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Francis , Mikita Lipski , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: David Francis With DSC, bpp can be fractional in multiples of 1/16. Change drm_dp_calc_pbn_mode to reflect this, adding a new parameter bool dsc. When this parameter is true, treat the bpp parameter as having units not of bits per pixel, but 1/16 of a bit per pixel v2: Don't add separate function for this v3: Keep the calculation in a single equation Cc: Lyude Paul Reviewed-by: Manasi Navare Reviewed-by: Lyude Paul Reviewed-by: Harry Wentland Signed-off-by: David Francis Signed-off-by: Mikita Lipski Reported-by: kbuild test robot --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/drm_dp_mst_topology.c | 38 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +- drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +- drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- include/drm/drm_dp_mst_helper.h | 3 +- 6 files changed, 43 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 455c51c38720..9fc03fc1017d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4967,7 +4967,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, is_y420); bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; clock = adjusted_mode->clock; - dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp); + dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); } dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state, mst_mgr, diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index ae5809a1f19a..261e2c1828c6 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -4342,10 +4342,11 @@ EXPORT_SYMBOL(drm_dp_check_act_status); * drm_dp_calc_pbn_mode() - Calculate the PBN for a mode. * @clock: dot clock for the mode * @bpp: bpp for the mode. + * @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel * * This uses the formula in the spec to calculate the PBN value for a mode. */ -int drm_dp_calc_pbn_mode(int clock, int bpp) +int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) { /* * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006 @@ -4356,12 +4357,47 @@ int drm_dp_calc_pbn_mode(int clock, int bpp) * peak_kbps *= (1006/1000) * peak_kbps *= (64/54) * peak_kbps *= 8 convert to bytes + * + * If the bpp is in units of 1/16, further divide by 16. Put this + * factor in the numerator rather than the denominator to avoid + * integer overflow */ + + if (dsc) + return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 / 16), + 8 * 54 * 1000 * 1000); + return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006), 8 * 54 * 1000 * 1000); + } EXPORT_SYMBOL(drm_dp_calc_pbn_mode); +static int test_calc_pbn_mode(void) +{ + int ret; + ret = drm_dp_calc_pbn_mode(154000, 30, false); + if (ret != 689) { + DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, expected PBN %d, actual PBN %d.\n", + 154000, 30, 689, ret); + return -EINVAL; + } + ret = drm_dp_calc_pbn_mode(234000, 30, false); + if (ret != 1047) { + DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, expected PBN %d, actual PBN %d.\n", + 234000, 30, 1047, ret); + return -EINVAL; + } + ret = drm_dp_calc_pbn_mode(297000, 24, false); + if (ret != 1063) { + DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, expected PBN %d, actual PBN %d.\n", + 297000, 24, 1063, ret); + return -EINVAL; + } + return 0; +} + + /* we want to kick the TX after we've ack the up/down IRQs. */ static void drm_dp_mst_kick_tx(struct drm_dp_mst_topology_mgr *mgr) { diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 03d1cba0b696..92be17711287 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -61,7 +61,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, crtc_state->pipe_bpp = bpp; crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, - crtc_state->pipe_bpp); + crtc_state->pipe_bpp, + false); slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, port, crtc_state->pbn); diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 549486f1d937..1c9e23d5a6fd 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -782,7 +782,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder, const int bpp = connector->display_info.bpc * 3; const int clock = crtc_state->adjusted_mode.clock; - asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, bpp); + asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, bpp, false); } slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c b/drivers/gpu/drm/radeon/radeon_dp_mst.c index ee28f5b3785e..28eef9282874 100644 --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c @@ -518,7 +518,7 @@ static bool radeon_mst_mode_fixup(struct drm_encoder *encoder, mst_enc = radeon_encoder->enc_priv; - mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp); + mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp, false); mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices; DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index d5fc90b30487..68656913cfe5 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -719,8 +719,7 @@ bool drm_dp_mst_port_has_audio(struct drm_dp_mst_topology_mgr *mgr, struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port); -int drm_dp_calc_pbn_mode(int clock, int bpp); - +int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc); bool drm_dp_mst_allocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int pbn, int slots);