| Message ID | 157541985531.46157.16935250205964640126.stgit@naples-babu.amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | APIC ID fixes for AMD EPYC CPU models | expand |
On Tue, 03 Dec 2019 18:37:35 -0600 Babu Moger <babu.moger@amd.com> wrote: > Introduce last level cache id(llc_id) in x86CPU topology. This information is > required to build the topology in EPIC mode. can you add a reference to spec here so one could look for detailed information about this? > Signed-off-by: Babu Moger <babu.moger@amd.com> > --- > hw/core/machine-hmp-cmds.c | 3 +++ > hw/core/machine.c | 13 +++++++++++++ > hw/i386/pc.c | 10 ++++++++++ > include/hw/i386/topology.h | 1 + > qapi/machine.json | 7 +++++-- > target/i386/cpu.c | 2 ++ > target/i386/cpu.h | 1 + > 7 files changed, 35 insertions(+), 2 deletions(-) > > diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c > index cd970cc4c5..59c91d1ce1 100644 > --- a/hw/core/machine-hmp-cmds.c > +++ b/hw/core/machine-hmp-cmds.c > @@ -90,6 +90,9 @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict) > if (c->has_die_id) { > monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id); > } > + if (c->has_llc_id) { > + monitor_printf(mon, " llc-id: \"%" PRIu64 "\"\n", c->llc_id); > + } > if (c->has_core_id) { > monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id); > } > diff --git a/hw/core/machine.c b/hw/core/machine.c > index e59b181ead..ff991e6ab5 100644 > --- a/hw/core/machine.c > +++ b/hw/core/machine.c > @@ -683,6 +683,11 @@ void machine_set_cpu_numa_node(MachineState *machine, > return; > } > > + if (props->has_llc_id && !slot->props.has_llc_id) { > + error_setg(errp, "llc-id is not supported"); > + return; > + } > + > /* skip slots with explicit mismatch */ > if (props->has_thread_id && props->thread_id != slot->props.thread_id) { > continue; > @@ -696,6 +701,10 @@ void machine_set_cpu_numa_node(MachineState *machine, > continue; > } > > + if (props->has_llc_id && props->llc_id != slot->props.llc_id) { > + continue; > + } > + > if (props->has_socket_id && props->socket_id != slot->props.socket_id) { > continue; > } > @@ -1034,6 +1043,10 @@ static char *cpu_slot_to_string(const CPUArchId *cpu) > if (cpu->props.has_die_id) { > g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); > } > + > + if (cpu->props.has_llc_id) { > + g_string_append_printf(s, "llc-id: %"PRId64, cpu->props.llc_id); > + } > if (cpu->props.has_core_id) { > if (s->len) { > g_string_append_printf(s, ", "); > diff --git a/hw/i386/pc.c b/hw/i386/pc.c > index 17de152a77..df5339c102 100644 > --- a/hw/i386/pc.c > +++ b/hw/i386/pc.c > @@ -2294,6 +2294,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, > > topo_ids.pkg_id = cpu->socket_id; > topo_ids.die_id = cpu->die_id; > + topo_ids.llc_id = cpu->llc_id; > topo_ids.core_id = cpu->core_id; > topo_ids.smt_id = cpu->thread_id; > cpu->apic_id = apicid_from_topo_ids(&topo_info, &topo_ids); > @@ -2339,6 +2340,13 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, > } > cpu->die_id = topo_ids.die_id; > > + if (cpu->llc_id != -1 && cpu->llc_id != topo_ids.llc_id) { > + error_setg(errp, "property llc-id: %u doesn't match set apic-id:" > + " 0x%x (llc-id: %u)", cpu->llc_id, cpu->apic_id, topo_ids.llc_id); > + return; > + } > + cpu->llc_id = topo_ids.llc_id; > + > if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { > error_setg(errp, "property core-id: %u doesn't match set apic-id:" > " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo_ids.core_id); > @@ -2752,6 +2760,8 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) > ms->possible_cpus->cpus[i].props.has_die_id = true; > ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id; > } > + ms->possible_cpus->cpus[i].props.has_llc_id = true; > + ms->possible_cpus->cpus[i].props.llc_id = topo_ids.llc_id; > ms->possible_cpus->cpus[i].props.has_core_id = true; > ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id; > ms->possible_cpus->cpus[i].props.has_thread_id = true; > diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h > index ba52d49079..1238006208 100644 > --- a/include/hw/i386/topology.h > +++ b/include/hw/i386/topology.h > @@ -48,6 +48,7 @@ typedef uint32_t apic_id_t; > typedef struct X86CPUTopoIDs { > unsigned pkg_id; > unsigned die_id; > + unsigned llc_id; > unsigned core_id; > unsigned smt_id; > } X86CPUTopoIDs; > diff --git a/qapi/machine.json b/qapi/machine.json > index ca26779f1a..1ca5b73418 100644 > --- a/qapi/machine.json > +++ b/qapi/machine.json > @@ -646,9 +646,11 @@ > # @node-id: NUMA node ID the CPU belongs to > # @socket-id: socket number within node/board the CPU belongs to > # @die-id: die number within node/board the CPU belongs to (Since 4.1) > -# @core-id: core number within die the CPU belongs to# @thread-id: thread number within core the CPU belongs to > +# @llc-id: last level cache number within node/board the CPU belongs to (Since 4.2) > +# @core-id: core number within die the CPU belongs to > +# @thread-id: thread number within core the CPU belongs to > # > -# Note: currently there are 5 properties that could be present > +# Note: currently there are 6 properties that could be present > # but management should be prepared to pass through other > # properties with device_add command to allow for future > # interface extension. This also requires the filed names to be kept in > @@ -660,6 +662,7 @@ > 'data': { '*node-id': 'int', > '*socket-id': 'int', > '*die-id': 'int', > + '*llc-id': 'int', > '*core-id': 'int', > '*thread-id': 'int' > } > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index bc9b491557..3c81aa3ecd 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -6222,12 +6222,14 @@ static Property x86_cpu_properties[] = { > DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), > DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), > DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), > + DEFINE_PROP_INT32("llc-id", X86CPU, llc_id, 0), > DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), > #else > DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), > DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), > DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), > DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), > + DEFINE_PROP_INT32("llc-id", X86CPU, llc_id, -1), > DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), > #endif > DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index af57fda8e5..a56d44e405 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -1711,6 +1711,7 @@ struct X86CPU { > int32_t node_id; /* NUMA node this CPU belongs to */ > int32_t socket_id; > int32_t die_id; > + int32_t llc_id; > int32_t core_id; > int32_t thread_id; > > >
On 12/3/19 6:37 PM, Babu Moger wrote: > Introduce last level cache id(llc_id) in x86CPU topology. This information is > required to build the topology in EPIC mode. > > Signed-off-by: Babu Moger <babu.moger@amd.com> > --- > +++ b/qapi/machine.json > @@ -646,9 +646,11 @@ > # @node-id: NUMA node ID the CPU belongs to > # @socket-id: socket number within node/board the CPU belongs to > # @die-id: die number within node/board the CPU belongs to (Since 4.1) > -# @core-id: core number within die the CPU belongs to# @thread-id: thread number within core the CPU belongs to > +# @llc-id: last level cache number within node/board the CPU belongs to (Since 4.2) s/4.2/5.0/ > +# @core-id: core number within die the CPU belongs to > +# @thread-id: thread number within core the CPU belongs to > # > -# Note: currently there are 5 properties that could be present > +# Note: currently there are 6 properties that could be present > # but management should be prepared to pass through other > # properties with device_add command to allow for future > # interface extension. This also requires the filed names to be kept in > @@ -660,6 +662,7 @@ > 'data': { '*node-id': 'int', > '*socket-id': 'int', > '*die-id': 'int', > + '*llc-id': 'int', > '*core-id': 'int', > '*thread-id': 'int' > }
On 1/28/20 10:27 AM, Igor Mammedov wrote: > On Tue, 03 Dec 2019 18:37:35 -0600 > Babu Moger <babu.moger@amd.com> wrote: > >> Introduce last level cache id(llc_id) in x86CPU topology. This information is >> required to build the topology in EPIC mode. > can you add a reference to spec here so one could look for > detailed information about this? Yes. Will add it next series. > > >> Signed-off-by: Babu Moger <babu.moger@amd.com> >> --- >> hw/core/machine-hmp-cmds.c | 3 +++ >> hw/core/machine.c | 13 +++++++++++++ >> hw/i386/pc.c | 10 ++++++++++ >> include/hw/i386/topology.h | 1 + >> qapi/machine.json | 7 +++++-- >> target/i386/cpu.c | 2 ++ >> target/i386/cpu.h | 1 + >> 7 files changed, 35 insertions(+), 2 deletions(-) >> >> diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c >> index cd970cc4c5..59c91d1ce1 100644 >> --- a/hw/core/machine-hmp-cmds.c >> +++ b/hw/core/machine-hmp-cmds.c >> @@ -90,6 +90,9 @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict) >> if (c->has_die_id) { >> monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id); >> } >> + if (c->has_llc_id) { >> + monitor_printf(mon, " llc-id: \"%" PRIu64 "\"\n", c->llc_id); >> + } >> if (c->has_core_id) { >> monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id); >> } >> diff --git a/hw/core/machine.c b/hw/core/machine.c >> index e59b181ead..ff991e6ab5 100644 >> --- a/hw/core/machine.c >> +++ b/hw/core/machine.c >> @@ -683,6 +683,11 @@ void machine_set_cpu_numa_node(MachineState *machine, >> return; >> } >> >> + if (props->has_llc_id && !slot->props.has_llc_id) { >> + error_setg(errp, "llc-id is not supported"); >> + return; >> + } >> + >> /* skip slots with explicit mismatch */ >> if (props->has_thread_id && props->thread_id != slot->props.thread_id) { >> continue; >> @@ -696,6 +701,10 @@ void machine_set_cpu_numa_node(MachineState *machine, >> continue; >> } >> >> + if (props->has_llc_id && props->llc_id != slot->props.llc_id) { >> + continue; >> + } >> + >> if (props->has_socket_id && props->socket_id != slot->props.socket_id) { >> continue; >> } >> @@ -1034,6 +1043,10 @@ static char *cpu_slot_to_string(const CPUArchId *cpu) >> if (cpu->props.has_die_id) { >> g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); >> } >> + >> + if (cpu->props.has_llc_id) { >> + g_string_append_printf(s, "llc-id: %"PRId64, cpu->props.llc_id); >> + } >> if (cpu->props.has_core_id) { >> if (s->len) { >> g_string_append_printf(s, ", "); >> diff --git a/hw/i386/pc.c b/hw/i386/pc.c >> index 17de152a77..df5339c102 100644 >> --- a/hw/i386/pc.c >> +++ b/hw/i386/pc.c >> @@ -2294,6 +2294,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, >> >> topo_ids.pkg_id = cpu->socket_id; >> topo_ids.die_id = cpu->die_id; >> + topo_ids.llc_id = cpu->llc_id; >> topo_ids.core_id = cpu->core_id; >> topo_ids.smt_id = cpu->thread_id; >> cpu->apic_id = apicid_from_topo_ids(&topo_info, &topo_ids); >> @@ -2339,6 +2340,13 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, >> } >> cpu->die_id = topo_ids.die_id; >> >> + if (cpu->llc_id != -1 && cpu->llc_id != topo_ids.llc_id) { >> + error_setg(errp, "property llc-id: %u doesn't match set apic-id:" >> + " 0x%x (llc-id: %u)", cpu->llc_id, cpu->apic_id, topo_ids.llc_id); >> + return; >> + } >> + cpu->llc_id = topo_ids.llc_id; >> + >> if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { >> error_setg(errp, "property core-id: %u doesn't match set apic-id:" >> " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo_ids.core_id); >> @@ -2752,6 +2760,8 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) >> ms->possible_cpus->cpus[i].props.has_die_id = true; >> ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id; >> } >> + ms->possible_cpus->cpus[i].props.has_llc_id = true; >> + ms->possible_cpus->cpus[i].props.llc_id = topo_ids.llc_id; >> ms->possible_cpus->cpus[i].props.has_core_id = true; >> ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id; >> ms->possible_cpus->cpus[i].props.has_thread_id = true; >> diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h >> index ba52d49079..1238006208 100644 >> --- a/include/hw/i386/topology.h >> +++ b/include/hw/i386/topology.h >> @@ -48,6 +48,7 @@ typedef uint32_t apic_id_t; >> typedef struct X86CPUTopoIDs { >> unsigned pkg_id; >> unsigned die_id; >> + unsigned llc_id; >> unsigned core_id; >> unsigned smt_id; >> } X86CPUTopoIDs; >> diff --git a/qapi/machine.json b/qapi/machine.json >> index ca26779f1a..1ca5b73418 100644 >> --- a/qapi/machine.json >> +++ b/qapi/machine.json >> @@ -646,9 +646,11 @@ >> # @node-id: NUMA node ID the CPU belongs to >> # @socket-id: socket number within node/board the CPU belongs to >> # @die-id: die number within node/board the CPU belongs to (Since 4.1) >> -# @core-id: core number within die the CPU belongs to# @thread-id: thread number within core the CPU belongs to >> +# @llc-id: last level cache number within node/board the CPU belongs to (Since 4.2) >> +# @core-id: core number within die the CPU belongs to >> +# @thread-id: thread number within core the CPU belongs to >> # >> -# Note: currently there are 5 properties that could be present >> +# Note: currently there are 6 properties that could be present >> # but management should be prepared to pass through other >> # properties with device_add command to allow for future >> # interface extension. This also requires the filed names to be kept in >> @@ -660,6 +662,7 @@ >> 'data': { '*node-id': 'int', >> '*socket-id': 'int', >> '*die-id': 'int', >> + '*llc-id': 'int', >> '*core-id': 'int', >> '*thread-id': 'int' >> } >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c >> index bc9b491557..3c81aa3ecd 100644 >> --- a/target/i386/cpu.c >> +++ b/target/i386/cpu.c >> @@ -6222,12 +6222,14 @@ static Property x86_cpu_properties[] = { >> DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), >> DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), >> DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), >> + DEFINE_PROP_INT32("llc-id", X86CPU, llc_id, 0), >> DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), >> #else >> DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), >> DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), >> DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), >> DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), >> + DEFINE_PROP_INT32("llc-id", X86CPU, llc_id, -1), >> DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), >> #endif >> DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), >> diff --git a/target/i386/cpu.h b/target/i386/cpu.h >> index af57fda8e5..a56d44e405 100644 >> --- a/target/i386/cpu.h >> +++ b/target/i386/cpu.h >> @@ -1711,6 +1711,7 @@ struct X86CPU { >> int32_t node_id; /* NUMA node this CPU belongs to */ >> int32_t socket_id; >> int32_t die_id; >> + int32_t llc_id; >> int32_t core_id; >> int32_t thread_id; >> >> >> >
On 1/28/20 10:31 AM, Eric Blake wrote: > On 12/3/19 6:37 PM, Babu Moger wrote: >> Introduce last level cache id(llc_id) in x86CPU topology. This >> information is >> required to build the topology in EPIC mode. >> >> Signed-off-by: Babu Moger <babu.moger@amd.com> >> --- > >> +++ b/qapi/machine.json >> @@ -646,9 +646,11 @@ >> # @node-id: NUMA node ID the CPU belongs to >> # @socket-id: socket number within node/board the CPU belongs to >> # @die-id: die number within node/board the CPU belongs to (Since 4.1) >> -# @core-id: core number within die the CPU belongs to# @thread-id: >> thread number within core the CPU belongs to >> +# @llc-id: last level cache number within node/board the CPU belongs to >> (Since 4.2) > > s/4.2/5.0/ Sure. Will change it. Thanks > >> +# @core-id: core number within die the CPU belongs to >> +# @thread-id: thread number within core the CPU belongs to >> # >> -# Note: currently there are 5 properties that could be present >> +# Note: currently there are 6 properties that could be present >> # but management should be prepared to pass through other >> # properties with device_add command to allow for future >> # interface extension. This also requires the filed names to be kept in >> @@ -660,6 +662,7 @@ >> 'data': { '*node-id': 'int', >> '*socket-id': 'int', >> '*die-id': 'int', >> + '*llc-id': 'int', >> '*core-id': 'int', >> '*thread-id': 'int' >> }
diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c index cd970cc4c5..59c91d1ce1 100644 --- a/hw/core/machine-hmp-cmds.c +++ b/hw/core/machine-hmp-cmds.c @@ -90,6 +90,9 @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict) if (c->has_die_id) { monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id); } + if (c->has_llc_id) { + monitor_printf(mon, " llc-id: \"%" PRIu64 "\"\n", c->llc_id); + } if (c->has_core_id) { monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id); } diff --git a/hw/core/machine.c b/hw/core/machine.c index e59b181ead..ff991e6ab5 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -683,6 +683,11 @@ void machine_set_cpu_numa_node(MachineState *machine, return; } + if (props->has_llc_id && !slot->props.has_llc_id) { + error_setg(errp, "llc-id is not supported"); + return; + } + /* skip slots with explicit mismatch */ if (props->has_thread_id && props->thread_id != slot->props.thread_id) { continue; @@ -696,6 +701,10 @@ void machine_set_cpu_numa_node(MachineState *machine, continue; } + if (props->has_llc_id && props->llc_id != slot->props.llc_id) { + continue; + } + if (props->has_socket_id && props->socket_id != slot->props.socket_id) { continue; } @@ -1034,6 +1043,10 @@ static char *cpu_slot_to_string(const CPUArchId *cpu) if (cpu->props.has_die_id) { g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); } + + if (cpu->props.has_llc_id) { + g_string_append_printf(s, "llc-id: %"PRId64, cpu->props.llc_id); + } if (cpu->props.has_core_id) { if (s->len) { g_string_append_printf(s, ", "); diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 17de152a77..df5339c102 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -2294,6 +2294,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, topo_ids.pkg_id = cpu->socket_id; topo_ids.die_id = cpu->die_id; + topo_ids.llc_id = cpu->llc_id; topo_ids.core_id = cpu->core_id; topo_ids.smt_id = cpu->thread_id; cpu->apic_id = apicid_from_topo_ids(&topo_info, &topo_ids); @@ -2339,6 +2340,13 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, } cpu->die_id = topo_ids.die_id; + if (cpu->llc_id != -1 && cpu->llc_id != topo_ids.llc_id) { + error_setg(errp, "property llc-id: %u doesn't match set apic-id:" + " 0x%x (llc-id: %u)", cpu->llc_id, cpu->apic_id, topo_ids.llc_id); + return; + } + cpu->llc_id = topo_ids.llc_id; + if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) { error_setg(errp, "property core-id: %u doesn't match set apic-id:" " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo_ids.core_id); @@ -2752,6 +2760,8 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) ms->possible_cpus->cpus[i].props.has_die_id = true; ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id; } + ms->possible_cpus->cpus[i].props.has_llc_id = true; + ms->possible_cpus->cpus[i].props.llc_id = topo_ids.llc_id; ms->possible_cpus->cpus[i].props.has_core_id = true; ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id; ms->possible_cpus->cpus[i].props.has_thread_id = true; diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index ba52d49079..1238006208 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -48,6 +48,7 @@ typedef uint32_t apic_id_t; typedef struct X86CPUTopoIDs { unsigned pkg_id; unsigned die_id; + unsigned llc_id; unsigned core_id; unsigned smt_id; } X86CPUTopoIDs; diff --git a/qapi/machine.json b/qapi/machine.json index ca26779f1a..1ca5b73418 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -646,9 +646,11 @@ # @node-id: NUMA node ID the CPU belongs to # @socket-id: socket number within node/board the CPU belongs to # @die-id: die number within node/board the CPU belongs to (Since 4.1) -# @core-id: core number within die the CPU belongs to# @thread-id: thread number within core the CPU belongs to +# @llc-id: last level cache number within node/board the CPU belongs to (Since 4.2) +# @core-id: core number within die the CPU belongs to +# @thread-id: thread number within core the CPU belongs to # -# Note: currently there are 5 properties that could be present +# Note: currently there are 6 properties that could be present # but management should be prepared to pass through other # properties with device_add command to allow for future # interface extension. This also requires the filed names to be kept in @@ -660,6 +662,7 @@ 'data': { '*node-id': 'int', '*socket-id': 'int', '*die-id': 'int', + '*llc-id': 'int', '*core-id': 'int', '*thread-id': 'int' } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index bc9b491557..3c81aa3ecd 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6222,12 +6222,14 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), + DEFINE_PROP_INT32("llc-id", X86CPU, llc_id, 0), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), #else DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), + DEFINE_PROP_INT32("llc-id", X86CPU, llc_id, -1), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), #endif DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index af57fda8e5..a56d44e405 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1711,6 +1711,7 @@ struct X86CPU { int32_t node_id; /* NUMA node this CPU belongs to */ int32_t socket_id; int32_t die_id; + int32_t llc_id; int32_t core_id; int32_t thread_id;
Introduce last level cache id(llc_id) in x86CPU topology. This information is required to build the topology in EPIC mode. Signed-off-by: Babu Moger <babu.moger@amd.com> --- hw/core/machine-hmp-cmds.c | 3 +++ hw/core/machine.c | 13 +++++++++++++ hw/i386/pc.c | 10 ++++++++++ include/hw/i386/topology.h | 1 + qapi/machine.json | 7 +++++-- target/i386/cpu.c | 2 ++ target/i386/cpu.h | 1 + 7 files changed, 35 insertions(+), 2 deletions(-)