arm64: dts: rockchip: Describe PX30 caches
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Message ID 20191204103940.22050-1-miquel.raynal@bootlin.com
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  • arm64: dts: rockchip: Describe PX30 caches
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Miquel Raynal Dec. 4, 2019, 10:39 a.m. UTC
PX30 SoCs feature 4 Cortex-A35 CPUs with each of them a L1 data and
instruction cache. Both are 32kiB wide (PX30 TRM) and made of 64-bit
lines (ARM Cortex-A35 manual). I-cache is 2-way set associative (ARM
Cortex-A35 manual), D-cache is 4-way set associative (ARM
Cortex-A35manual).

An L2 cache is placed after these 4 L1 caches (PX30 TRM), is 256kiB
wide (PX30 TRM) and made of 64-bit lines (ARM Cortex-A35 manual) and
is 8-way set associative (ARM Cortex-A35 manual).

Describe all of them in the PX30 DTSI.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 arch/arm64/boot/dts/rockchip/px30.dtsi | 35 ++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

Comments

Peter Geis Dec. 4, 2019, 3:36 p.m. UTC | #1
On Wed, Dec 4, 2019 at 5:40 AM Miquel Raynal <miquel.raynal@bootlin.com> wrote:
>
> PX30 SoCs feature 4 Cortex-A35 CPUs with each of them a L1 data and
> instruction cache. Both are 32kiB wide (PX30 TRM) and made of 64-bit
> lines (ARM Cortex-A35 manual). I-cache is 2-way set associative (ARM
> Cortex-A35 manual), D-cache is 4-way set associative (ARM
> Cortex-A35manual).
>
> An L2 cache is placed after these 4 L1 caches (PX30 TRM), is 256kiB
> wide (PX30 TRM) and made of 64-bit lines (ARM Cortex-A35 manual) and
> is 8-way set associative (ARM Cortex-A35 manual).
>
> Describe all of them in the PX30 DTSI.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
>  arch/arm64/boot/dts/rockchip/px30.dtsi | 35 ++++++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
> index 1fd12bd09e83..0e10a224a84b 100644
> --- a/arch/arm64/boot/dts/rockchip/px30.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
> @@ -48,6 +48,13 @@
>                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
>                         dynamic-power-coefficient = <90>;
>                         operating-points-v2 = <&cpu0_opp_table>;
> +                       i-cache-size = <0x8000>;
> +                       i-cache-line-size = <64>;
> +                       i-cache-sets = <256>;
> +                       d-cache-size = <0x8000>;
> +                       d-cache-line-size = <64>;
> +                       d-cache-sets = <128>;
> +                       next-level-cache = <&l2>;

If the i-cache is 2-way associative and the d-cache is 4-way, wouldn't
that mean these two values are backwards?

>                 };
>
>                 cpu1: cpu@1 {
> @@ -60,6 +67,13 @@
>                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
>                         dynamic-power-coefficient = <90>;
>                         operating-points-v2 = <&cpu0_opp_table>;
> +                       i-cache-size = <0x8000>;
> +                       i-cache-line-size = <64>;
> +                       i-cache-sets = <256>;
> +                       d-cache-size = <0x8000>;
> +                       d-cache-line-size = <64>;
> +                       d-cache-sets = <128>;
> +                       next-level-cache = <&l2>;
>                 };
>
>                 cpu2: cpu@2 {
> @@ -72,6 +86,13 @@
>                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
>                         dynamic-power-coefficient = <90>;
>                         operating-points-v2 = <&cpu0_opp_table>;
> +                       i-cache-size = <0x8000>;
> +                       i-cache-line-size = <64>;
> +                       i-cache-sets = <256>;
> +                       d-cache-size = <0x8000>;
> +                       d-cache-line-size = <64>;
> +                       d-cache-sets = <128>;
> +                       next-level-cache = <&l2>;
>                 };
>
>                 cpu3: cpu@3 {
> @@ -84,6 +105,13 @@
>                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
>                         dynamic-power-coefficient = <90>;
>                         operating-points-v2 = <&cpu0_opp_table>;
> +                       i-cache-size = <0x8000>;
> +                       i-cache-line-size = <64>;
> +                       i-cache-sets = <256>;
> +                       d-cache-size = <0x8000>;
> +                       d-cache-line-size = <64>;
> +                       d-cache-sets = <128>;
> +                       next-level-cache = <&l2>;
>                 };
>
>                 idle-states {
> @@ -107,6 +135,13 @@
>                                 min-residency-us = <2000>;
>                         };
>                 };
> +
> +               l2: l2-cache {
> +                       compatible = "cache";
> +                       cache-size = <0x40000>;
> +                       cache-line-size = <64>;
> +                       cache-sets = <512>;
> +               };
>         };
>
>         cpu0_opp_table: cpu0-opp-table {
> --
> 2.20.1
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
Miquel Raynal Dec. 4, 2019, 3:44 p.m. UTC | #2
Hi Peter,

Peter Geis <pgwipeout@gmail.com> wrote on Wed, 4 Dec 2019 10:36:19
-0500:

> On Wed, Dec 4, 2019 at 5:40 AM Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> >
> > PX30 SoCs feature 4 Cortex-A35 CPUs with each of them a L1 data and
> > instruction cache. Both are 32kiB wide (PX30 TRM) and made of 64-bit
> > lines (ARM Cortex-A35 manual). I-cache is 2-way set associative (ARM
> > Cortex-A35 manual), D-cache is 4-way set associative (ARM
> > Cortex-A35manual).
> >
> > An L2 cache is placed after these 4 L1 caches (PX30 TRM), is 256kiB
> > wide (PX30 TRM) and made of 64-bit lines (ARM Cortex-A35 manual) and
> > is 8-way set associative (ARM Cortex-A35 manual).
> >
> > Describe all of them in the PX30 DTSI.
> >
> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> > ---
> >  arch/arm64/boot/dts/rockchip/px30.dtsi | 35 ++++++++++++++++++++++++++
> >  1 file changed, 35 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
> > index 1fd12bd09e83..0e10a224a84b 100644
> > --- a/arch/arm64/boot/dts/rockchip/px30.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
> > @@ -48,6 +48,13 @@
> >                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> >                         dynamic-power-coefficient = <90>;
> >                         operating-points-v2 = <&cpu0_opp_table>;
> > +                       i-cache-size = <0x8000>;
> > +                       i-cache-line-size = <64>;
> > +                       i-cache-sets = <256>;
> > +                       d-cache-size = <0x8000>;
> > +                       d-cache-line-size = <64>;
> > +                       d-cache-sets = <128>;
> > +                       next-level-cache = <&l2>;  
> 
> If the i-cache is 2-way associative and the d-cache is 4-way, wouldn't
> that mean these two values are backwards?

Which value are you referring to? Do you mean cache-sets? The following
calculation is my understanding of the situation but it is the first
time I am doing it so I might be totally wrong.

My understanding is that if there are 32768 cache bytes made of 64-byte
lines, so there are 512 lines in both cases.

Then, if the instruction cache is 2-way associative, it means there are
512 / 2 = 256 sets. For the data cache (4-way), it would be 512 / 4 =
128. Am I wrong?

Thanks,
Miquèl
Peter Geis Dec. 4, 2019, 5:14 p.m. UTC | #3
On Wed, Dec 4, 2019 at 10:44 AM Miquel Raynal <miquel.raynal@bootlin.com> wrote:
>
> Hi Peter,
>
> Peter Geis <pgwipeout@gmail.com> wrote on Wed, 4 Dec 2019 10:36:19
> -0500:
>
> > On Wed, Dec 4, 2019 at 5:40 AM Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> > >
> > > PX30 SoCs feature 4 Cortex-A35 CPUs with each of them a L1 data and
> > > instruction cache. Both are 32kiB wide (PX30 TRM) and made of 64-bit
> > > lines (ARM Cortex-A35 manual). I-cache is 2-way set associative (ARM
> > > Cortex-A35 manual), D-cache is 4-way set associative (ARM
> > > Cortex-A35manual).
> > >
> > > An L2 cache is placed after these 4 L1 caches (PX30 TRM), is 256kiB
> > > wide (PX30 TRM) and made of 64-bit lines (ARM Cortex-A35 manual) and
> > > is 8-way set associative (ARM Cortex-A35 manual).
> > >
> > > Describe all of them in the PX30 DTSI.
> > >
> > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> > > ---
> > >  arch/arm64/boot/dts/rockchip/px30.dtsi | 35 ++++++++++++++++++++++++++
> > >  1 file changed, 35 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
> > > index 1fd12bd09e83..0e10a224a84b 100644
> > > --- a/arch/arm64/boot/dts/rockchip/px30.dtsi
> > > +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
> > > @@ -48,6 +48,13 @@
> > >                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> > >                         dynamic-power-coefficient = <90>;
> > >                         operating-points-v2 = <&cpu0_opp_table>;
> > > +                       i-cache-size = <0x8000>;
> > > +                       i-cache-line-size = <64>;
> > > +                       i-cache-sets = <256>;
> > > +                       d-cache-size = <0x8000>;
> > > +                       d-cache-line-size = <64>;
> > > +                       d-cache-sets = <128>;
> > > +                       next-level-cache = <&l2>;
> >
> > If the i-cache is 2-way associative and the d-cache is 4-way, wouldn't
> > that mean these two values are backwards?
>
> Which value are you referring to? Do you mean cache-sets? The following
> calculation is my understanding of the situation but it is the first
> time I am doing it so I might be totally wrong.
>
> My understanding is that if there are 32768 cache bytes made of 64-byte
> lines, so there are 512 lines in both cases.
>
> Then, if the instruction cache is 2-way associative, it means there are
> 512 / 2 = 256 sets. For the data cache (4-way), it would be 512 / 4 =
> 128. Am I wrong?

Apologies, you are correct, it was I who was mistaken.
>
> Thanks,
> Miquèl
Miquel Raynal Dec. 4, 2019, 5:17 p.m. UTC | #4
Hi Peter,

Peter Geis <pgwipeout@gmail.com> wrote on Wed, 4 Dec 2019 12:14:40
-0500:

> On Wed, Dec 4, 2019 at 10:44 AM Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> >
> > Hi Peter,
> >
> > Peter Geis <pgwipeout@gmail.com> wrote on Wed, 4 Dec 2019 10:36:19
> > -0500:
> >  
> > > On Wed, Dec 4, 2019 at 5:40 AM Miquel Raynal <miquel.raynal@bootlin.com> wrote:  
> > > >
> > > > PX30 SoCs feature 4 Cortex-A35 CPUs with each of them a L1 data and
> > > > instruction cache. Both are 32kiB wide (PX30 TRM) and made of 64-bit
> > > > lines (ARM Cortex-A35 manual). I-cache is 2-way set associative (ARM
> > > > Cortex-A35 manual), D-cache is 4-way set associative (ARM
> > > > Cortex-A35manual).
> > > >
> > > > An L2 cache is placed after these 4 L1 caches (PX30 TRM), is 256kiB
> > > > wide (PX30 TRM) and made of 64-bit lines (ARM Cortex-A35 manual) and
> > > > is 8-way set associative (ARM Cortex-A35 manual).
> > > >
> > > > Describe all of them in the PX30 DTSI.
> > > >
> > > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> > > > ---
> > > >  arch/arm64/boot/dts/rockchip/px30.dtsi | 35 ++++++++++++++++++++++++++
> > > >  1 file changed, 35 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
> > > > index 1fd12bd09e83..0e10a224a84b 100644
> > > > --- a/arch/arm64/boot/dts/rockchip/px30.dtsi
> > > > +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
> > > > @@ -48,6 +48,13 @@
> > > >                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> > > >                         dynamic-power-coefficient = <90>;
> > > >                         operating-points-v2 = <&cpu0_opp_table>;
> > > > +                       i-cache-size = <0x8000>;
> > > > +                       i-cache-line-size = <64>;
> > > > +                       i-cache-sets = <256>;
> > > > +                       d-cache-size = <0x8000>;
> > > > +                       d-cache-line-size = <64>;
> > > > +                       d-cache-sets = <128>;
> > > > +                       next-level-cache = <&l2>;  
> > >
> > > If the i-cache is 2-way associative and the d-cache is 4-way, wouldn't
> > > that mean these two values are backwards?  
> >
> > Which value are you referring to? Do you mean cache-sets? The following
> > calculation is my understanding of the situation but it is the first
> > time I am doing it so I might be totally wrong.
> >
> > My understanding is that if there are 32768 cache bytes made of 64-byte
> > lines, so there are 512 lines in both cases.
> >
> > Then, if the instruction cache is 2-way associative, it means there are
> > 512 / 2 = 256 sets. For the data cache (4-way), it would be 512 / 4 =
> > 128. Am I wrong?  
> 
> Apologies, you are correct, it was I who was mistaken.

No problem, I was not 100% sure either. Thanks for the review anyway!

Cheers,
Miquèl
Heiko Stuebner Dec. 20, 2019, 12:55 a.m. UTC | #5
Am Mittwoch, 4. Dezember 2019, 11:39:40 CET schrieb Miquel Raynal:
> PX30 SoCs feature 4 Cortex-A35 CPUs with each of them a L1 data and
> instruction cache. Both are 32kiB wide (PX30 TRM) and made of 64-bit
> lines (ARM Cortex-A35 manual). I-cache is 2-way set associative (ARM
> Cortex-A35 manual), D-cache is 4-way set associative (ARM
> Cortex-A35manual).
> 
> An L2 cache is placed after these 4 L1 caches (PX30 TRM), is 256kiB
> wide (PX30 TRM) and made of 64-bit lines (ARM Cortex-A35 manual) and
> is 8-way set associative (ARM Cortex-A35 manual).
> 
> Describe all of them in the PX30 DTSI.
> 
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
>  arch/arm64/boot/dts/rockchip/px30.dtsi | 35 ++++++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
> index 1fd12bd09e83..0e10a224a84b 100644
> --- a/arch/arm64/boot/dts/rockchip/px30.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
> @@ -48,6 +48,13 @@
>  			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
>  			dynamic-power-coefficient = <90>;
>  			operating-points-v2 = <&cpu0_opp_table>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2>;
>  		};
>  
>  		cpu1: cpu@1 {
> @@ -60,6 +67,13 @@
>  			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
>  			dynamic-power-coefficient = <90>;
>  			operating-points-v2 = <&cpu0_opp_table>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2>;
>  		};
>  
>  		cpu2: cpu@2 {
> @@ -72,6 +86,13 @@
>  			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
>  			dynamic-power-coefficient = <90>;
>  			operating-points-v2 = <&cpu0_opp_table>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2>;
>  		};
>  
>  		cpu3: cpu@3 {
> @@ -84,6 +105,13 @@
>  			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
>  			dynamic-power-coefficient = <90>;
>  			operating-points-v2 = <&cpu0_opp_table>;
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2>;
>  		};
>  
>  		idle-states {
> @@ -107,6 +135,13 @@
>  				min-residency-us = <2000>;
>  			};
>  		};
> +
> +		l2: l2-cache {
> +			compatible = "cache";
> +			cache-size = <0x40000>;
> +			cache-line-size = <64>;
> +			cache-sets = <512>;
> +		};
>  	};

Looks like Rob did answer my unspoken question, citing his reply to
	"arm64: dts: amazon: add Amazon's Annapurna Labs Alpine v3 support" [0]

"We only define cache attributes if not discoverable or the cache ID 
registers are wrong and you need to override what's discoverable."

So unless the cache information read during boot is wrong, it looks
like we don't need this.

Heiko


[0] https://patchwork.kernel.org/patch/11279705/
Miquel Raynal Dec. 23, 2019, 9:03 a.m. UTC | #6
Hi Heiko,

Heiko Stübner <heiko@sntech.de> wrote on Fri, 20 Dec 2019 01:55:58
+0100:

> Am Mittwoch, 4. Dezember 2019, 11:39:40 CET schrieb Miquel Raynal:
> > PX30 SoCs feature 4 Cortex-A35 CPUs with each of them a L1 data and
> > instruction cache. Both are 32kiB wide (PX30 TRM) and made of 64-bit
> > lines (ARM Cortex-A35 manual). I-cache is 2-way set associative (ARM
> > Cortex-A35 manual), D-cache is 4-way set associative (ARM
> > Cortex-A35manual).
> > 
> > An L2 cache is placed after these 4 L1 caches (PX30 TRM), is 256kiB
> > wide (PX30 TRM) and made of 64-bit lines (ARM Cortex-A35 manual) and
> > is 8-way set associative (ARM Cortex-A35 manual).
> > 
> > Describe all of them in the PX30 DTSI.
> > 
> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> > ---
> >  arch/arm64/boot/dts/rockchip/px30.dtsi | 35 ++++++++++++++++++++++++++
> >  1 file changed, 35 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
> > index 1fd12bd09e83..0e10a224a84b 100644
> > --- a/arch/arm64/boot/dts/rockchip/px30.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
> > @@ -48,6 +48,13 @@
> >  			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> >  			dynamic-power-coefficient = <90>;
> >  			operating-points-v2 = <&cpu0_opp_table>;
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2>;
> >  		};
> >  
> >  		cpu1: cpu@1 {
> > @@ -60,6 +67,13 @@
> >  			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> >  			dynamic-power-coefficient = <90>;
> >  			operating-points-v2 = <&cpu0_opp_table>;
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2>;
> >  		};
> >  
> >  		cpu2: cpu@2 {
> > @@ -72,6 +86,13 @@
> >  			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> >  			dynamic-power-coefficient = <90>;
> >  			operating-points-v2 = <&cpu0_opp_table>;
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2>;
> >  		};
> >  
> >  		cpu3: cpu@3 {
> > @@ -84,6 +105,13 @@
> >  			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
> >  			dynamic-power-coefficient = <90>;
> >  			operating-points-v2 = <&cpu0_opp_table>;
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2>;
> >  		};
> >  
> >  		idle-states {
> > @@ -107,6 +135,13 @@
> >  				min-residency-us = <2000>;
> >  			};
> >  		};
> > +
> > +		l2: l2-cache {
> > +			compatible = "cache";
> > +			cache-size = <0x40000>;
> > +			cache-line-size = <64>;
> > +			cache-sets = <512>;
> > +		};
> >  	};  
> 
> Looks like Rob did answer my unspoken question, citing his reply to
> 	"arm64: dts: amazon: add Amazon's Annapurna Labs Alpine v3 support" [0]
> 
> "We only define cache attributes if not discoverable or the cache ID 
> registers are wrong and you need to override what's discoverable."
> 
> So unless the cache information read during boot is wrong, it looks
> like we don't need this.

Well, I actually met the:

         "Unable to detect cache hierarchy for CPU <x>"

warning in the dmesg. Do you know anything about cache ID registers?

There is some kind of "i-cache" infos [TRM page 391] but it doesn't
seem enough to describe the cache hierarchy.

> 
> Heiko
> 
> 
> [0] https://patchwork.kernel.org/patch/11279705/

Thanks,
Miquèl

Patch
diff mbox series

diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 1fd12bd09e83..0e10a224a84b 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -48,6 +48,13 @@ 
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 			dynamic-power-coefficient = <90>;
 			operating-points-v2 = <&cpu0_opp_table>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2>;
 		};
 
 		cpu1: cpu@1 {
@@ -60,6 +67,13 @@ 
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 			dynamic-power-coefficient = <90>;
 			operating-points-v2 = <&cpu0_opp_table>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2>;
 		};
 
 		cpu2: cpu@2 {
@@ -72,6 +86,13 @@ 
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 			dynamic-power-coefficient = <90>;
 			operating-points-v2 = <&cpu0_opp_table>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2>;
 		};
 
 		cpu3: cpu@3 {
@@ -84,6 +105,13 @@ 
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 			dynamic-power-coefficient = <90>;
 			operating-points-v2 = <&cpu0_opp_table>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2>;
 		};
 
 		idle-states {
@@ -107,6 +135,13 @@ 
 				min-residency-us = <2000>;
 			};
 		};
+
+		l2: l2-cache {
+			compatible = "cache";
+			cache-size = <0x40000>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+		};
 	};
 
 	cpu0_opp_table: cpu0-opp-table {