drm/i915/gt: Replace I915_READ with intel_uncore_read
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Message ID 20191205162428.1503-1-andi.shyti@intel.com
State New
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Series
  • drm/i915/gt: Replace I915_READ with intel_uncore_read
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Commit Message

Andi Shyti Dec. 5, 2019, 4:24 p.m. UTC
Get rid of the last remaining I915_READ in gt/ and make gt-land
the first I915_READ-free happy island.

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index df3369c3f330..4da53aa3d8e2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -155,6 +155,7 @@  static const struct engine_info intel_engines[] = {
  */
 u32 intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
 {
+	struct intel_uncore *uncore = &dev_priv->uncore;
 	u32 cxt_size;
 
 	BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
@@ -178,11 +179,11 @@  u32 intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
 			if (IS_HASWELL(dev_priv))
 				return HSW_CXT_TOTAL_SIZE;
 
-			cxt_size = I915_READ(GEN7_CXT_SIZE);
+			ctx_size = intel_uncore_read(uncore, GEN7_CXT_SIZE);
 			return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
 					PAGE_SIZE);
 		case 6:
-			cxt_size = I915_READ(CXT_SIZE);
+			ctx_size = intel_uncore_read(uncore, CXT_SIZE);
 			return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
 					PAGE_SIZE);
 		case 5:
@@ -197,7 +198,7 @@  u32 intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
 			 * minimum allocation anyway so it should all come
 			 * out in the wash.
 			 */
-			cxt_size = I915_READ(CXT_SIZE) + 1;
+			ctx_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
 			DRM_DEBUG_DRIVER("gen%d CXT_SIZE = %d bytes [0x%08x]\n",
 					 INTEL_GEN(dev_priv),
 					 cxt_size * 64,