[4/4] arm64: dts: qcom: c630: Enable display
diff mbox series

Message ID 20191207203553.286017-5-robdclark@gmail.com
State New
Headers show
Series
  • drm+dt: multi panel selection and yoga c630 display
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Commit Message

Rob Clark Dec. 7, 2019, 8:35 p.m. UTC
From: Bjorn Andersson <bjorn.andersson@linaro.org>

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
[Initial patch from Bjorn, I've added some regulator-boot-on's to
 account for display related regulators enabled by the firmware,
 and updated to handle the two possible panels that can be installed.]
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
 .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 165 ++++++++++++++++++
 1 file changed, 165 insertions(+)

Patch
diff mbox series

diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
index 13dc619687f3..459f65e3eb53 100644
--- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
+++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
@@ -7,6 +7,7 @@ 
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include "sdm845.dtsi"
 #include "pm8998.dtsi"
@@ -18,6 +19,70 @@ 
 	aliases {
 		hsuart0 = &uart6;
 	};
+
+	ivo_panel {
+		compatible = "ivo,m133nwf4-r0";
+		panel-id = <0xc5>;
+		status = "disabled";
+		power-supply = <&vlcm_3v3>;
+		no-hpd;
+
+		ports {
+			port {
+				ivo_panel_in_edp: endpoint {
+					remote-endpoint = <&sn65dsi86_out_ivo>;
+				};
+			};
+		};
+	};
+
+	boe_panel {
+		compatible = "boe,nv133fhm-n61";
+		panel-id = <0xc4>;
+		status = "disabled";
+		power-supply = <&vlcm_3v3>;
+		no-hpd;
+
+		ports {
+			port {
+				boe_panel_in_edp: endpoint {
+					remote-endpoint = <&sn65dsi86_out_boe>;
+				};
+			};
+		};
+	};
+
+	vlcm_3v3: vlcm-3v3-power {
+		compatible = "regulator-fixed";
+		regulator-name = "VLCM_3V3";
+
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-boot-on;
+	};
+
+	sw_edp_1p2: sw-edp-1p2-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "SW_EDP_1P2";
+
+		vin-supply = <&vreg_l2a_1p2>;
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+
+		gpio = <&pm8998_gpio 9 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-boot-on;
+	};
+
+	sn65dsi86_refclk: sn65dsi86-refclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+
+		clock-frequency = <19200000>;
+	};
 };
 
 &adsp_pas {
@@ -79,6 +144,7 @@ 
 			regulator-min-microvolt = <880000>;
 			regulator-max-microvolt = <880000>;
 			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-boot-on;
 		};
 
 		vddpx_10:
@@ -216,6 +282,7 @@ 
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1208000>;
 			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-boot-on;
 		};
 
 		vreg_l28a_3p0: ldo28 {
@@ -239,6 +306,25 @@ 
 	status = "okay";
 };
 
+&dsi0 {
+	status = "okay";
+	vdda-supply = <&vreg_l26a_1p2>;
+
+	ports {
+		port@1 {
+			endpoint {
+				remote-endpoint = <&sn65dsi86_in_a>;
+				data-lanes = <0 1 2 3>;
+			};
+		};
+	};
+};
+
+&dsi0_phy {
+	status = "okay";
+	vdds-supply = <&vreg_l1a_0p875>;
+};
+
 &gcc {
 	protected-clocks = <GCC_QSPI_CORE_CLK>,
 			   <GCC_QSPI_CORE_CLK_SRC>,
@@ -290,6 +376,58 @@ 
 	};
 };
 
+&i2c10 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	sn65dsi86: bridge@2c {
+		compatible = "ti,sn65dsi86";
+		reg = <0x2c>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&edp_bridge_en>, <&edp_bridge_irq>;
+
+		interrupts-extended = <&tlmm 10 IRQ_TYPE_LEVEL_HIGH>;
+
+		enable-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+
+		vpll-supply = <&vreg_l14a_1p88>;
+		vccio-supply = <&vreg_l14a_1p88>;
+		vcca-supply = <&sw_edp_1p2>;
+		vcc-supply = <&sw_edp_1p2>;
+
+		clocks = <&sn65dsi86_refclk>;
+		clock-names = "refclk";
+
+		max-brightness = <255>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				sn65dsi86_in_a: endpoint {
+					remote-endpoint = <&dsi0_out>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				sn65dsi86_out_ivo: endpoint@c5 {
+					reg = <0>;
+					remote-endpoint = <&ivo_panel_in_edp>;
+				};
+
+				sn65dsi86_out_boe: endpoint@c4 {
+					reg = <1>;
+					remote-endpoint = <&boe_panel_in_edp>;
+				};
+			};
+		};
+	};
+};
+
 &i2c11 {
 	status = "okay";
 	clock-frequency = <400000>;
@@ -306,6 +444,14 @@ 
 	};
 };
 
+&mdss {
+	status = "okay";
+};
+
+&mdss_mdp {
+	status = "okay";
+};
+
 &mss_pil {
 	firmware-name = "qcom/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/LENOVO/81JL/qcdsp2850.mbn";
 };
@@ -338,6 +484,14 @@ 
 	};
 };
 
+&qup_i2c10_default {
+	pinconf {
+		pins = "gpio55", "gpio56";
+		drive-strength = <2>;
+		bias-disable;
+	};
+};
+
 &qupv3_id_0 {
 	status = "okay";
 };
@@ -349,6 +503,17 @@ 
 &tlmm {
 	gpio-reserved-ranges = <0 4>, <81 4>;
 
+	edp_bridge_en: edp-bridge-enable {
+		pins = "gpio96";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	edp_bridge_irq: edp-bridge-irq {
+		pins = "gpio10";
+		bias-pull-down;
+	};
+
 	i2c2_hid_active: i2c2-hid-active {
 		pins = <37>;
 		function = "gpio";