| Message ID | 20191207203603.2314424-2-bjorn.andersson@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: qcom: gcc-msm8996: Fix CLKREF parenting | expand |
On Sat, 7 Dec 2019 12:36:02 -0800, Bjorn Andersson wrote: > The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the > SoC. Update the definition of these clocks to allow this to be wired up > to the appropriate clock source. > > Retain "xo" as the global named parent to make the change a nop in the > event that DT doesn't carry the necessary clocks definition. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > .../devicetree/bindings/clock/qcom,gcc.yaml | 6 ++-- > drivers/clk/qcom/gcc-msm8996.c | 35 +++++++++++++++---- > 2 files changed, 32 insertions(+), 9 deletions(-) > Acked-by: Rob Herring <robh@kernel.org>
Quoting Bjorn Andersson (2019-12-07 12:36:02) > The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the > SoC. Update the definition of these clocks to allow this to be wired up > to the appropriate clock source. > > Retain "xo" as the global named parent to make the change a nop in the > event that DT doesn't carry the necessary clocks definition. Something seems wrong still. I wonder if we need to add the XO "active only" clk to the rpm clk driver(s) and mark it as CLK_IS_CRITICAL. In theory that is really the truth for most of the SoCs out there because it's the only crystal that needs to be on all the time when the CPU is active. The "normal" XO clk will then be on all the time unless deep idle is entered and nobody has turned that on via some clk_prepare() call. That's because we root all other clks through the "normal" XO clk that will be on in deep idle/suspend if someone needs it to be. Did the downstream code explicitly enable this ln_bb_clk in the phy drivers? I think it may have?
On Wed 18 Dec 22:37 PST 2019, Stephen Boyd wrote: > Quoting Bjorn Andersson (2019-12-07 12:36:02) > > The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the > > SoC. Update the definition of these clocks to allow this to be wired up > > to the appropriate clock source. > > > > Retain "xo" as the global named parent to make the change a nop in the > > event that DT doesn't carry the necessary clocks definition. > > Something seems wrong still. > > I wonder if we need to add the XO "active only" clk to the rpm clk > driver(s) and mark it as CLK_IS_CRITICAL. In theory that is really the > truth for most of the SoCs out there because it's the only crystal that > needs to be on all the time when the CPU is active. The "normal" XO clk > will then be on all the time unless deep idle is entered and nobody has > turned that on via some clk_prepare() call. That's because we root all > other clks through the "normal" XO clk that will be on in deep > idle/suspend if someone needs it to be. > The patch doesn't attempt to address the fact that our representation of XO is incomplete, only the fact that CXO2 isn't properly described. Looking at the clock distribution, we do have RPM_SMD_BB_CLK1_A which presumably is the clock you're referring to here - i.e. the clock resource connected to CXO. > Did the downstream code explicitly enable this ln_bb_clk in the phy > drivers? I think it may have? > Yes, afaict all downstream drivers consuming a CLKREF also consumes LN_BB and ensures that this is enabled. So we've been relying on UFS to either not have probed yet or that UFS probed successfully for PCIe and USB to be functional. So either we need this patch to ensure that the requests propagates down, or I need to patch up the PHY drivers to ensure that they also vote for the PMIC clock - and I do prefer this patch. Regards, Bjorn
Quoting Bjorn Andersson (2019-12-19 18:34:27) > On Wed 18 Dec 22:37 PST 2019, Stephen Boyd wrote: > > > Quoting Bjorn Andersson (2019-12-07 12:36:02) > > > The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the > > > SoC. Update the definition of these clocks to allow this to be wired up > > > to the appropriate clock source. > > > > > > Retain "xo" as the global named parent to make the change a nop in the > > > event that DT doesn't carry the necessary clocks definition. > > > > Something seems wrong still. > > > > I wonder if we need to add the XO "active only" clk to the rpm clk > > driver(s) and mark it as CLK_IS_CRITICAL. In theory that is really the > > truth for most of the SoCs out there because it's the only crystal that > > needs to be on all the time when the CPU is active. The "normal" XO clk > > will then be on all the time unless deep idle is entered and nobody has > > turned that on via some clk_prepare() call. That's because we root all > > other clks through the "normal" XO clk that will be on in deep > > idle/suspend if someone needs it to be. > > > > The patch doesn't attempt to address the fact that our representation of > XO is incomplete, only the fact that CXO2 isn't properly described. > > Looking at the clock distribution, we do have RPM_SMD_BB_CLK1_A which > presumably is the clock you're referring to here - i.e. the clock > resource connected to CXO. I don't mean the buffer clks, but the XO resource specifically. It's the representation to the RPM that deep sleep/deep idle should or shouldn't turn off XO and achieve "XO shutdown". Basically it can never be off when the CPU is active because then the CPU itself wouldn't be clocked, but when the CPU isn't active we may want to turn it off if nothing is using it during sleep to clock some sort of wakeup logic or device that is active when the CPU is idle. > > > Did the downstream code explicitly enable this ln_bb_clk in the phy > > drivers? I think it may have? > > > > Yes, afaict all downstream drivers consuming a CLKREF also consumes > LN_BB and ensures that this is enabled. So we've been relying on UFS to > either not have probed yet or that UFS probed successfully for PCIe and > USB to be functional. > > So either we need this patch to ensure that the requests propagates > down, or I need to patch up the PHY drivers to ensure that they also > vote for the PMIC clock - and I do prefer this patch. Cool. Yeah seems better to just indicate that the reference clks are clocked by something else and fix that problem now.
Quoting Bjorn Andersson (2019-12-07 12:36:02) > The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the > SoC. Update the definition of these clocks to allow this to be wired up > to the appropriate clock source. > > Retain "xo" as the global named parent to make the change a nop in the > event that DT doesn't carry the necessary clocks definition. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > .../devicetree/bindings/clock/qcom,gcc.yaml | 6 ++-- > drivers/clk/qcom/gcc-msm8996.c | 35 +++++++++++++++---- > 2 files changed, 32 insertions(+), 9 deletions(-) What is this patch based on? I think I'm missing some sort of 8996 yaml gcc binding patch.
On Mon 23 Dec 18:48 PST 2019, Stephen Boyd wrote: > Quoting Bjorn Andersson (2019-12-07 12:36:02) > > The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the > > SoC. Update the definition of these clocks to allow this to be wired up > > to the appropriate clock source. > > > > Retain "xo" as the global named parent to make the change a nop in the > > event that DT doesn't carry the necessary clocks definition. > > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > --- > > .../devicetree/bindings/clock/qcom,gcc.yaml | 6 ++-- > > drivers/clk/qcom/gcc-msm8996.c | 35 +++++++++++++++---- > > 2 files changed, 32 insertions(+), 9 deletions(-) > > What is this patch based on? I think I'm missing some sort of 8996 yaml > gcc binding patch. > The patch applies cleanly on linux-next and afaict it depends on the yamlification done in 9de7269e9703 ("dt-bindings: clock: Add YAML schemas for the QCOM GCC clock bindings"), which git tells me is included in v5.5-rc1 as well. Am I misunderstanding your question? Regards, Bjorn
Quoting Bjorn Andersson (2019-12-26 14:23:15) > On Mon 23 Dec 18:48 PST 2019, Stephen Boyd wrote: > > > Quoting Bjorn Andersson (2019-12-07 12:36:02) > > > The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the > > > SoC. Update the definition of these clocks to allow this to be wired up > > > to the appropriate clock source. > > > > > > Retain "xo" as the global named parent to make the change a nop in the > > > event that DT doesn't carry the necessary clocks definition. > > > > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > > --- > > > .../devicetree/bindings/clock/qcom,gcc.yaml | 6 ++-- > > > drivers/clk/qcom/gcc-msm8996.c | 35 +++++++++++++++---- > > > 2 files changed, 32 insertions(+), 9 deletions(-) > > > > What is this patch based on? I think I'm missing some sort of 8996 yaml > > gcc binding patch. > > > > The patch applies cleanly on linux-next and afaict it depends on the > yamlification done in 9de7269e9703 ("dt-bindings: clock: Add YAML > schemas for the QCOM GCC clock bindings"), which git tells me is > included in v5.5-rc1 as well. > > Am I misunderstanding your question? > There doesn't seem to be any sort of minitems or maxitems in my yaml binding file for the clocks or clock-names properties.
On Mon 23 Dec 18:20 PST 2019, Stephen Boyd wrote: > Quoting Bjorn Andersson (2019-12-19 18:34:27) > > On Wed 18 Dec 22:37 PST 2019, Stephen Boyd wrote: > > > > > Quoting Bjorn Andersson (2019-12-07 12:36:02) > > > > The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the > > > > SoC. Update the definition of these clocks to allow this to be wired up > > > > to the appropriate clock source. > > > > > > > > Retain "xo" as the global named parent to make the change a nop in the > > > > event that DT doesn't carry the necessary clocks definition. > > > > > > Something seems wrong still. > > > > > > I wonder if we need to add the XO "active only" clk to the rpm clk > > > driver(s) and mark it as CLK_IS_CRITICAL. In theory that is really the > > > truth for most of the SoCs out there because it's the only crystal that > > > needs to be on all the time when the CPU is active. The "normal" XO clk > > > will then be on all the time unless deep idle is entered and nobody has > > > turned that on via some clk_prepare() call. That's because we root all > > > other clks through the "normal" XO clk that will be on in deep > > > idle/suspend if someone needs it to be. > > > > > > > The patch doesn't attempt to address the fact that our representation of > > XO is incomplete, only the fact that CXO2 isn't properly described. > > > > Looking at the clock distribution, we do have RPM_SMD_BB_CLK1_A which > > presumably is the clock you're referring to here - i.e. the clock > > resource connected to CXO. > > I don't mean the buffer clks, but the XO resource specifically. It's the > representation to the RPM that deep sleep/deep idle should or shouldn't > turn off XO and achieve "XO shutdown". Basically it can never be off > when the CPU is active because then the CPU itself wouldn't be clocked, > but when the CPU isn't active we may want to turn it off if nothing is > using it during sleep to clock some sort of wakeup logic or device that > is active when the CPU is idle. > I see. So we're missing the representation of the "raw" CXO in clk-smd-rpm.c, and I'm lacking some understanding of how these pieces should be tied together for us to realize the "XO shutdown"... > > > > > Did the downstream code explicitly enable this ln_bb_clk in the phy > > > drivers? I think it may have? > > > > > > > Yes, afaict all downstream drivers consuming a CLKREF also consumes > > LN_BB and ensures that this is enabled. So we've been relying on UFS to > > either not have probed yet or that UFS probed successfully for PCIe and > > USB to be functional. > > > > So either we need this patch to ensure that the requests propagates > > down, or I need to patch up the PHY drivers to ensure that they also > > vote for the PMIC clock - and I do prefer this patch. > > Cool. Yeah seems better to just indicate that the reference clks are > clocked by something else and fix that problem now. > Let me know if I shouldn't interpret this sentence as "let's merge this for now". Regards, Bjorn
Quoting Bjorn Andersson (2019-12-26 14:41:56) > On Mon 23 Dec 18:20 PST 2019, Stephen Boyd wrote: > > > Quoting Bjorn Andersson (2019-12-19 18:34:27) > > > On Wed 18 Dec 22:37 PST 2019, Stephen Boyd wrote: > > > > > > > Quoting Bjorn Andersson (2019-12-07 12:36:02) > > > > > The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the > > > > > SoC. Update the definition of these clocks to allow this to be wired up > > > > > to the appropriate clock source. > > > > > > > > > > Retain "xo" as the global named parent to make the change a nop in the > > > > > event that DT doesn't carry the necessary clocks definition. > > > > > > > > Something seems wrong still. > > > > > > > > I wonder if we need to add the XO "active only" clk to the rpm clk > > > > driver(s) and mark it as CLK_IS_CRITICAL. In theory that is really the > > > > truth for most of the SoCs out there because it's the only crystal that > > > > needs to be on all the time when the CPU is active. The "normal" XO clk > > > > will then be on all the time unless deep idle is entered and nobody has > > > > turned that on via some clk_prepare() call. That's because we root all > > > > other clks through the "normal" XO clk that will be on in deep > > > > idle/suspend if someone needs it to be. > > > > > > > > > > The patch doesn't attempt to address the fact that our representation of > > > XO is incomplete, only the fact that CXO2 isn't properly described. > > > > > > Looking at the clock distribution, we do have RPM_SMD_BB_CLK1_A which > > > presumably is the clock you're referring to here - i.e. the clock > > > resource connected to CXO. > > > > I don't mean the buffer clks, but the XO resource specifically. It's the > > representation to the RPM that deep sleep/deep idle should or shouldn't > > turn off XO and achieve "XO shutdown". Basically it can never be off > > when the CPU is active because then the CPU itself wouldn't be clocked, > > but when the CPU isn't active we may want to turn it off if nothing is > > using it during sleep to clock some sort of wakeup logic or device that > > is active when the CPU is idle. > > > > I see. So we're missing the representation of the "raw" CXO in > clk-smd-rpm.c, and I'm lacking some understanding of how these pieces > should be tied together for us to realize the "XO shutdown"... Ok. This is another topic so not important to this patch right now. > > > > > > > > Did the downstream code explicitly enable this ln_bb_clk in the phy > > > > drivers? I think it may have? > > > > > > > > > > Yes, afaict all downstream drivers consuming a CLKREF also consumes > > > LN_BB and ensures that this is enabled. So we've been relying on UFS to > > > either not have probed yet or that UFS probed successfully for PCIe and > > > USB to be functional. > > > > > > So either we need this patch to ensure that the requests propagates > > > down, or I need to patch up the PHY drivers to ensure that they also > > > vote for the PMIC clock - and I do prefer this patch. > > > > Cool. Yeah seems better to just indicate that the reference clks are > > clocked by something else and fix that problem now. > > > > Let me know if I shouldn't interpret this sentence as "let's merge this > for now". Yes I'd like to merge for now but the binding needs to be adjusted. Please resend.
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index e73a56fb60ca..f8bd902d4e6d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -41,19 +41,21 @@ properties: clocks: minItems: 1 - maxItems: 3 + maxItems: 4 items: - description: Board XO source - description: Board active XO source - description: Sleep clock source + - description: Second XO source clock-names: minItems: 1 - maxItems: 3 + maxItems: 4 items: - const: bi_tcxo - const: bi_tcxo_ao - const: sleep_clk + - const: cxo2 '#clock-cells': const: 1 diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c index d004cdaa0e39..3c3a7ff04562 100644 --- a/drivers/clk/qcom/gcc-msm8996.c +++ b/drivers/clk/qcom/gcc-msm8996.c @@ -3046,7 +3046,10 @@ static struct clk_branch gcc_usb3_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_clkref_clk", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo2", + .name = "xo", + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3060,7 +3063,10 @@ static struct clk_branch gcc_hdmi_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_hdmi_clkref_clk", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo2", + .name = "xo", + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3074,7 +3080,10 @@ static struct clk_branch gcc_edp_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_edp_clkref_clk", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo2", + .name = "xo", + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3088,7 +3097,10 @@ static struct clk_branch gcc_ufs_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_ufs_clkref_clk", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo2", + .name = "xo", + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3102,7 +3114,10 @@ static struct clk_branch gcc_pcie_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_clkref_clk", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo2", + .name = "xo", + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3116,7 +3131,10 @@ static struct clk_branch gcc_rx2_usb2_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_rx2_usb2_clkref_clk", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo2", + .name = "xo", + }, .num_parents = 1, .ops = &clk_branch2_ops, }, @@ -3130,7 +3148,10 @@ static struct clk_branch gcc_rx1_usb2_clkref_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_rx1_usb2_clkref_clk", - .parent_names = (const char *[]){ "xo" }, + .parent_data = &(const struct clk_parent_data){ + .fw_name = "cxo2", + .name = "xo", + }, .num_parents = 1, .ops = &clk_branch2_ops, },
The CLKREF clocks are all fed by the clock signal on the CXO2 pad on the SoC. Update the definition of these clocks to allow this to be wired up to the appropriate clock source. Retain "xo" as the global named parent to make the change a nop in the event that DT doesn't carry the necessary clocks definition. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- .../devicetree/bindings/clock/qcom,gcc.yaml | 6 ++-- drivers/clk/qcom/gcc-msm8996.c | 35 +++++++++++++++---- 2 files changed, 32 insertions(+), 9 deletions(-)